Skip to content

Commit db2adf8

Browse files
seldridgeseldridge
committed
[FIRRTL] Cleanup CreateSiFiveMetadata tests, NFC
Make additional modifications to the `emit-metadata.mlir` test to test more features orthogonally. This includes a test of a zero-port memory (which apparently is not rejected by verification?) and a separate read-only memory test. This replaces a two-read memory (which is already covered with the original omnibus test) and the older read-only memory test. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
1 parent 30ee93d commit db2adf8

File tree

1 file changed

+102
-60
lines changed

1 file changed

+102
-60
lines changed

‎test/Dialect/FIRRTL/emit-metadata.mlir

Lines changed: 102 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -275,6 +275,9 @@ firrtl.circuit "top"
275275
// 2. The memory JSON file is created with the same information as (1).
276276
// 3. A configuration file that contains the shape of the memory.
277277
//
278+
// Checks are broken up to test each of these files individually. Later tests,
279+
// that need to check all three files use the same check structure.
280+
//
278281
// This does _not_ check anything related to the design-under-test (DUT) which,
279282
// due to the fact that this test has a `MarkDUTAnnotation`, will also generate
280283
// that metadata. DUT metadata is checked with an earlier test.
@@ -426,86 +429,125 @@ firrtl.circuit "Foo" {
426429

427430
// -----
428431

429-
// CHECK-LABEL: firrtl.circuit "DualReadsSMem"
430-
firrtl.circuit "DualReadsSMem" {
431-
firrtl.module @DualReadsSMem() {
432-
%0:12 = firrtl.instance DualReads_ext @DualReads_ext(
433-
in R0_addr: !firrtl.uint<4>,
434-
in R0_en: !firrtl.uint<1>,
435-
in R0_clk: !firrtl.clock,
436-
in R0_data: !firrtl.uint<42>,
437-
in R1_addr: !firrtl.uint<4>,
438-
in R1_en: !firrtl.uint<1>,
439-
in R1_clk: !firrtl.clock,
440-
in R1_data: !firrtl.uint<42>,
441-
in W0_addr: !firrtl.uint<4>,
442-
in W0_en: !firrtl.uint<1>,
443-
in W0_clk: !firrtl.clock,
444-
in W0_data: !firrtl.uint<42>
445-
)
432+
// Test that zero read, write, and read-write ports produce sane output.
433+
434+
firrtl.circuit "Foo" {
435+
firrtl.module private @m() {
436+
firrtl.instance m_ext @m_ext()
446437
}
447-
firrtl.memmodule @DualReads_ext(
448-
in R0_addr: !firrtl.uint<4>,
449-
in R0_en: !firrtl.uint<1>,
450-
in R0_clk: !firrtl.clock,
451-
in R0_data: !firrtl.uint<42>,
452-
in R1_addr: !firrtl.uint<4>,
453-
in R1_en: !firrtl.uint<1>,
454-
in R1_clk: !firrtl.clock,
455-
in R1_data: !firrtl.uint<42>,
456-
in W0_addr: !firrtl.uint<4>,
457-
in W0_en: !firrtl.uint<1>,
458-
in W0_clk: !firrtl.clock,
459-
in W0_data: !firrtl.uint<42>
460-
) attributes {
461-
dataWidth = 42 : ui32,
462-
depth = 12 : ui64,
438+
firrtl.memmodule private @m_ext() attributes {
439+
dataWidth = 8 : ui32,
440+
depth = 16 : ui64,
463441
extraPorts = [],
464442
maskBits = 1 : ui32,
465-
numReadPorts = 2 : ui32,
443+
numReadPorts = 0 : ui32,
444+
numWritePorts = 0 : ui32,
466445
numReadWritePorts = 0 : ui32,
467-
numWritePorts = 1 : ui32,
468446
readLatency = 1 : ui32,
469447
writeLatency = 1 : ui32
470448
}
471-
// CHECK{LITERAL}: sv.verbatim "[\0A {\0A \22module_name\22: \22{{0}}\22,\0A \22depth\22: 12,\0A \22width\22: 42,\0A \22masked\22: false,\0A \22read\22: 2,\0A \22write\22: 1,\0A \22readwrite\22: 0,\0A \22extra_ports\22: [],\0A \22hierarchy\22: [\0A \22{{1}}.DualReads_ext\22\0A ]\0A }\0A]"
472-
// CHECK: {symbols = [@DualReads_ext, @DualReadsSMem]}
473-
// CHECK{LITERAL}: sv.verbatim "name {{0}} depth 12 width 42 ports write,read,read\0A" {symbols = [@DualReads_ext]}
449+
firrtl.module @Baz() {
450+
firrtl.instance m sym @m @m()
451+
}
452+
firrtl.module @Bar() attributes {
453+
annotations = [
454+
{
455+
class = "sifive.enterprise.firrtl.MarkDUTAnnotation"
456+
}
457+
]
458+
} {
459+
firrtl.instance baz sym @baz @Baz()
460+
}
461+
firrtl.module @Foo() {
462+
firrtl.instance bar sym @bar @Bar()
463+
}
474464
}
475465

466+
//------------------------------------------------------------------ (1) OM Info
467+
// CHECK-LABEL: firrtl.class @MemoryMetadata({{.*$}}
468+
// CHECK: %[[memoryObject:.+]] = firrtl.object @MemorySchema
469+
// CHECK: %[[#zero:]] = firrtl.integer 0
470+
// CHECK-NEXT: %[[#r:]] = firrtl.object.subfield %[[memoryObject]][readPorts_in]
471+
// CHECK-NEXT: firrtl.propassign %[[#r]], %[[#zero]]
472+
// CHECK-NEXT: %[[#zero:]] = firrtl.integer 0
473+
// CHECK-NEXT: %[[#w:]] = firrtl.object.subfield %[[memoryObject]][writePorts_in]
474+
// CHECK-NEXT: firrtl.propassign %[[#w]], %[[#zero]]
475+
// CHECK-NEXT: %[[#zero:]] = firrtl.integer 0
476+
// CHECK-NEXT: %[[#rw:]] = firrtl.object.subfield %[[memoryObject]][readwritePorts_in]
477+
// CHECK-NEXT: firrtl.propassign %[[#rw]], %[[#zero]]
478+
479+
//-------------------------------------------------------------- (2) Memory JSON
480+
// CHECK-LABEL: emit.file "metadata{{/|\\\\}}seq_mems.json"
481+
// CHECK-NEXT: sv.verbatim
482+
// CHECK-SAME: \22read\22: 0
483+
// CHECK-SAME: \22write\22: 0
484+
// CHECK-SAME: \22readwrite\22: 0
485+
486+
//------------------------------------------------------- (3) Configuration File
487+
// CHECK-LABEL: emit.file "mems.conf"
488+
// CHECK-NEXT{LITERAL}: sv.verbatim "name {{0}} depth 16 width 8 ports \0A"
489+
476490
// -----
477491

478-
// CHECK-LABEL: firrtl.circuit "ReadOnlyMemory"
479-
firrtl.circuit "ReadOnlyMemory" {
480-
firrtl.module @ReadOnlyMemory() {
481-
%0:4 = firrtl.instance rom_ext sym @rom_ext_0 @rom_ext(
482-
in R0_addr: !firrtl.uint<9>,
483-
in R0_en: !firrtl.uint<1>,
484-
in R0_clk: !firrtl.clock,
485-
out R0_data: !firrtl.uint<32>
486-
)
492+
// Test that a read-only memory produces metadata.
493+
494+
firrtl.circuit "Foo" {
495+
firrtl.module private @m() {
496+
firrtl.instance m_ext @m_ext()
487497
}
488-
firrtl.memmodule @rom_ext(
489-
in R0_addr: !firrtl.uint<9>,
490-
in R0_en: !firrtl.uint<1>,
491-
in R0_clk: !firrtl.clock,
492-
out R0_data: !firrtl.uint<32>
493-
) attributes {
494-
dataWidth = 32 : ui32,
495-
depth = 512 : ui64,
498+
firrtl.memmodule private @m_ext() attributes {
499+
dataWidth = 8 : ui32,
500+
depth = 16 : ui64,
496501
extraPorts = [],
497-
maskBits = 0 : ui32,
502+
maskBits = 1 : ui32,
498503
numReadPorts = 1 : ui32,
499-
numReadWritePorts = 0 : ui32,
500504
numWritePorts = 0 : ui32,
505+
numReadWritePorts = 0 : ui32,
501506
readLatency = 1 : ui32,
502507
writeLatency = 1 : ui32
503508
}
504-
// CHECK{LITERAL}: sv.verbatim "[\0A {\0A \22module_name\22: \22{{0}}\22,\0A \22depth\22: 512,\0A \22width\22: 32,\0A \22masked\22: false,\0A \22read\22: 1,\0A \22write\22: 0,\0A \22readwrite\22: 0,\0A \22extra_ports\22: [],\0A \22hierarchy\22: [\0A \22{{1}}.rom_ext\22\0A ]\0A }\0A]"
505-
// CHECK: symbols = [@rom_ext, @ReadOnlyMemory]}
506-
// CHECK{LITERAL}: sv.verbatim "name {{0}} depth 512 width 32 ports read\0A" {symbols = [@rom_ext]}
509+
firrtl.module @Baz() {
510+
firrtl.instance m sym @m @m()
511+
}
512+
firrtl.module @Bar() attributes {
513+
annotations = [
514+
{
515+
class = "sifive.enterprise.firrtl.MarkDUTAnnotation"
516+
}
517+
]
518+
} {
519+
firrtl.instance baz sym @baz @Baz()
520+
}
521+
firrtl.module @Foo() {
522+
firrtl.instance bar sym @bar @Bar()
523+
}
507524
}
508525

526+
//------------------------------------------------------------------ (1) OM Info
527+
// CHECK-LABEL: firrtl.class @MemoryMetadata({{.*$}}
528+
// CHECK: %[[memoryObject:.+]] = firrtl.object @MemorySchema
529+
// CHECK: firrtl.object.subfield %[[memoryObject]][maskBits_in]
530+
// CHECK: %[[#one:]] = firrtl.integer 1
531+
// CHECK-NEXT: %[[#r:]] = firrtl.object.subfield %[[memoryObject]][readPorts_in]
532+
// CHECK-NEXT: firrtl.propassign %[[#r]], %[[#one]]
533+
// CHECK-NEXT: %[[#zero:]] = firrtl.integer 0
534+
// CHECK-NEXT: %[[#w:]] = firrtl.object.subfield %[[memoryObject]][writePorts_in]
535+
// CHECK-NEXT: firrtl.propassign %[[#w]], %[[#zero]]
536+
// CHECK-NEXT: %[[#zero:]] = firrtl.integer 0
537+
// CHECK-NEXT: %[[#rw:]] = firrtl.object.subfield %[[memoryObject]][readwritePorts_in]
538+
// CHECK-NEXT: firrtl.propassign %[[#rw]], %[[#zero]]
539+
540+
//-------------------------------------------------------------- (2) Memory JSON
541+
// CHECK-LABEL: emit.file "metadata{{/|\\\\}}seq_mems.json"
542+
// CHECK-NEXT: sv.verbatim
543+
// CHECK-SAME: \22read\22: 1
544+
// CHECK-SAME: \22write\22: 0
545+
// CHECK-SAME: \22readwrite\22: 0
546+
547+
//------------------------------------------------------- (3) Configuration File
548+
// CHECK-LABEL: emit.file "mems.conf"
549+
// CHECK-NEXT{LITERAL}: sv.verbatim "name {{0}} depth 16 width 8 ports read\0A"
550+
509551
// -----
510552

511553
// CHECK-LABEL: firrtl.circuit "top"

0 commit comments

Comments
 (0)