Firtool Release 1.33.0

EDIT: firtool 1.33.0 has a known issue in canonicalizers which causes a complication failure so please use firtool 1.34.0.

What's Changed

• [Arc] Add arc conversion pass by @fabianschuiki in #4697
• [FIRRTLFolds] Add a mux canonicalize pattern by @prithayan in #4720
• [ESI] Option to flatten struct messages by @teqdruid in #4712
• [PyCDE] Set dialect attributes on modules, expose flatten dialect attr by @teqdruid in #4723
• [ExportVerilog] More support for SV attributes by @uenoku in #4716
• LLVM bump by @dtzSiFive in #4704
• [FIRRTL][NFCI] Move RefType to ODS by @dtzSiFive in #4731
• Disable folder for 4734 by @darthscsi in #4735
• [Support] Move FirtoolPassInstrumentation to a support header, NFC by @uenoku in #4738
• [ExportVerilog] Lowering option to emit 'wire' in port list by @teqdruid in #4737
• [ESI] Add more flexibility to port names during lowering by @teqdruid in #4736
• [FIRRTL] Instrinsic Modules by @darthscsi in #4733
• [FIRRTL] Add a pass to convert VoB -> BoV conversion by @rwy7 in #4654
• [SV] Move emitAsComment to SVAttributeAttr; remove SVAttributesAttr by @fabianschuiki in #4743
• [ExportVerilog] Add KEEP attr to Vivado array index bug workaround by @fabianschuiki in #4744
• [CI] Swap build mode of gcc and clang by @uenoku in #4747
• [ExtractInstances] Fix nondeterminism by using MapVector. by @uenoku in #4749

Full Changelog: firtool-1.32.0...firtool-1.33.0

Firtool Release 1.32.0

Overview

• Implement an iterative Tarjan's SCC to detect cycles
• Fix insertion point for fieldID.
• Bump LLVM to top-of-tree
• Add a canonicalization to swap constant index and unknown index of array gets
• Tweak suggested release tags, suggest firtool over sifive.
• Handle all data-flow ops in FieldSource
• Make DUT module public
• Limit BitCast to passive output, fix non-passive input.
• Handle port dontTouch, add inner sym.
• Replace single-address memories with registers
• Propapate bin flags through icmp and variadic op canonicalizer
• Disable one folder for 25% end-to-end perf improvement.
• Fixups to avoid memory safety issues.
• Reduce dontTouch+zero-width error to warning.
• Improve MacOS published binaries and flow
• Allow wiring type-equivalent types.
• Add disallowArrayIndexInlining option
• Unshallow CIRCT clone in uploadBinaries workflow
• Use port locations for diagnostics, don't dump module.
• Add a workflow for building and uploading Python wheels.

What's Changed

• [CheckCombCycles] Implement an iterative Tarjan's SCC to detect cycles by @prithayan in #4642
• [ESI] Introduce pure_module.input and pure_module.output by @teqdruid in #4657
• [ESI] Lower pure modules into HW modules by @teqdruid in #4658
• [FIRRTL][LegacyWiring] Fix insertion point for fieldID. by @dtzSiFive in #4664
• Bump LLVM to top-of-tree by @seldridge in #4666
• [HW] Add a canonicalization to swap constant index and unknown index of array gets by @uenoku in #4668
• [cmake] Tweak suggested release tags, suggest firtool over sifive. by @dtzSiFive in #4676
• Handle all data-flow ops in FieldSource by @darthscsi in #4673
• silence warning by @darthscsi in #4678
• [LowerAnnotations] Make DUT module public by @uenoku in #4672
• Fix Combinational Component Builder by @andrewb1999 in #4680
• [FIRRTL] Limit BitCast to passive output, fix non-passive input. by @dtzSiFive in #4648
• [LowerToHW] Handle port dontTouch, add inner sym. by @dtzSiFive in #4675
• [MemOp] Replace single-address memories with registers by @nandor in #4687
• [ESI] [mostly NFC] Lower ports pass refactoring by @teqdruid in #4670
• [ESI] Initial FIFO signaling: read latency 0 style by @teqdruid in #4679
• [CombFolds] Propapate bin flags through icmp and variadic op canonicalizer by @uenoku in #4695
• [Arc] Add dialect by @fabianschuiki in #4681
• [Handshake] Fix incorrect operation deletion in EliminateCBranchIntoMux canonicalization pattern by @RamirezLucas in #4650
• [COMB] disable one folder for 25% end-to-end perf improvement. by @darthscsi in #4690
• [FIRRTL][FoldMemRegs] Fixups to avoid memory safety issues. by @dtzSiFive in #4702
• [LowerToHW] Reduce dontTouch+zero-width error to warning. by @dtzSiFive in #4703
• Improve MacOS published binaries and flow by @jackkoenig in #4701
• [LowerAnnotations] Allow wiring type-equivalent types. by @dtzSiFive in #4656
• [ExportVerilog] Add disallowArrayIndexInlining option by @fabianschuiki in #4706
• Unshallow CIRCT clone in uploadBinaries workflow by @jackkoenig in #4707
• [LowerToHW] Use port locations for diagnostics, don't dump module. by @dtzSiFive in #4708
• [PyCDE] Expose signaling and FIFO0 by @teqdruid in #4705
• [CI] Add a workflow for building and uploading Python wheels. by @mikeurbach in #4710
• [ESI] Add parameters to PureModule lowering by @teqdruid in #4711

Full Changelog: firtool-1.31.0...firtool-1.32.0

Firtool Release 1.31.0

What's Changed

• Bump llvm to 78056e2f2d9510d2ace42fe7e9eb60e5abe8a3e7 by @rwy7 in #4645
• [FIRRTL][MemOp] Removed unused bits from memories by @nandor in #4652
• [LowerTypes] Track public modules and force lowering properly by @uenoku in #4655
• [ESI] Add specification to build signals into SV interface or not by @teqdruid in #4653

Full Changelog: firtool-1.30.0...firtool-1.31.0

Firtool Release 1.30.0

What's Changed

• [Pipeline] Plumb values through the pipeline + Support multi-cycle Ops by @matth2k in #4414
• [PyCDE] Class based struct definitions by @teqdruid in #4607
• [PyCDE][NFC] Cleanups and renames by @teqdruid in #4610
• [FIRRTL][GC] Always generate the scope yaml file by @youngar in #4612
• [HW][MSFT] Fix creating modules with InOut typed ports by @youngar in #4583
• Bump LLVM to 95e49f5a74c9e79778a62cc58b15875613cf9e59. by @mikeurbach in #4609
• [PyCDE] Improve type string representations by @teqdruid in #4616
• [PyCDE][NFC] Create signals from Python objects through Types by @teqdruid in #4611
• [LowerToHW] Lower aggregate constant by @uenoku in #4608
• Add port location information to verilog output by @youngar in #4540
• Migrate to the new folding api by @rwy7 in #4619
• [LLVM] Bump for CVE-2022-24439 by @teqdruid in #4621
• [CHIRRTL][NFC] Indicate using new fold API to squelch warnings. by @dtzSiFive in #4627
• [GC] Update numXMRs statistic. by @dtzSiFive in #4628
• [HW][NFC] InnerRef: Remove unused method definition by @dtzSiFive in #4629
• [ExportVerilog][PrettifyVerilog] Fix exprInEventControl by @uenoku in #4625
• [FIRRTL][NFC] Remove unused port boring/LCA methods. by @dtzSiFive in #4630
• [firtool] Use CIRCT's StripDebInfo pass instead of upstream by @youngar in #4632
• [FIRRTL] Remove extra whitespace around optional attr dicts by @rwy7 in #4324
• [ESI] Baseline XRT support by @teqdruid in #4537
• [FIRRTL] Support Chisel loadMemoryFromFile and loadMemoryFromFileInline by @seldridge in #4622
• [LowerAnnotations] Resolve legacy wiring annotations as WiringProblems by @sam-shahrestani in #4496
• [HWLegalizeModules] Legalize aggregate constant by @uenoku in #4626
• [ESI] Introduce ESI pure module op by @teqdruid in #4633
• [PyCDE] ESI pure module entry by @teqdruid in #4635
• [ESI][Cosim Runner] Add support for running binaries by @teqdruid in #4639
• [SV][ETC] Name port after instance result name, as well. by @dtzSiFive in #4640
• [firtool][NFC] Test relative path searching for includes. by @dtzSiFive in #4641
• [FIRRTL][AddSeqMemPorts] Fix use of DenseMap entry after invalidated. by @dtzSiFive in #4643
• [FIRRTL] Simple points-to like analysis by @darthscsi in #4637

New Contributors

• @sam-shahrestani made their first contribution in #4496

Full Changelog: firtool-1.29.0...firtool-1.30.0

Firtool Release 1.29.0

What's Changed

• [ESI][Capnp] Build against libcapnp on Windows by @teqdruid in #4585
• [FIRRTL] Always create ExtractSeqMems extract file by @seldridge in #4587
• [PyCDE] Improvements to support internal design by @teqdruid in #4591
• [circt-reduce] Explicitly nest the passes by @prithayan in #4594
• [SystemC] Make func private in lit test. NFC by @prithayan in #4595
• [CI] Bump cmake version (new image) and switch to ninja by @teqdruid in #4597
• Bump LLVM submodule by @teqdruid in #4568
• [firtool][FIRRTL] Make Grand Central Collateral Synthesizable by @seldridge in #4599
• [Calyx] Add 'remove comb groups' pass by @mortbopet in #4522
• [Calyx] Add SCF -> Calyx -> FSM integration test by @mortbopet in #4598
• [NFC] Move from llvm::makeArrayRef to ArrayRef deduction guides by @boschmitt in #4601
• [ExportVerilog] Don't regard input ports as assignment patterns by @uenoku in #4603
• Add TAGS to gitignore by @adkian-sifive in #4602
• [HW] Add support for struct_explodeOp in HWToLLVM by @cepheus69 in #4519
• [CalyxToFSM] Add FSM-flow remove groups pass by @mortbopet in #4600
• [PyCDE] Type system refactoring by @teqdruid in #4604

New Contributors

• @boschmitt made their first contribution in #4601
• @adkian-sifive made their first contribution in #4602
• @cepheus69 made their first contribution in #4519

Full Changelog: firtool-1.28.0...firtool-1.29.0

SiFive Internal Release 1.5.4

What's Changed

• Backport "[LowerToHW] Add extra guards to header macros (#4469)" to sifive-1.5 by @uenoku in #4581

Full Changelog: sifive/1/5/3...sifive/1/5/4

SiFive Internal Release 1.22.4

What's Changed

• Backport "[LowerToHW] Add extra guards to header macros (#4469)" to sifive 1.22 by @uenoku in #4580

Full Changelog: sifive/1/22/3...sifive/1/22/4

Firtool Release 1.28.0

Summary

• Users can specify an include path to firtool using --include-dir <directory> as the long form of -I
• The FIRRTL parser no longer overrides port locations with module locations

What's Changed

• [FIRRTL] Use circuit location for annotation file parse errors. by @dtzSiFive in #4541
• [FIRRTL] Move FVectorType to ODS by @rwy7 in #4534
• [PyCDE] Add ControlReg construct by @teqdruid in #4536
• [FIRRTL] Move BundleType to ODS by @rwy7 in #4535
• [Python] Use the "private namespace" approach for mlir dep by @teqdruid in #4546
• [PyCDE][NFC] Hide the circt package in our namespace by @teqdruid in #4545
• [StandardToHandshake] Replace liveness analysis with SSA maximization by @RamirezLucas in #4520
• [PyCDE] Value -> Signal by @teqdruid in #4550
• [GC] Fail pass if emit errors about companion instantiation. by @dtzSiFive in #4552
• [FIRRTL] Mark DUT AddSeqMemPorts ports dontTouch by @seldridge in #4554
• [FIRRTL] Change FIRRTL fieldID fns to use uint64_t by @seldridge in #4528
• [CMake] Fix option CIRCT_LLHD_SIM_ENABLED by @SpriteOvO in #4555
• [FIRRTL] Move SIntType and UIntType to ODS by @rwy7 in #4529
• [PyCDE] Change module API to extend Module instead of using a decorator by @teqdruid in #4556
• [FIRRTL] Move enum attributes to dedicated td file by @rwy7 in #4562
• [SSP] Support OR-Tools-based schedulers in -ssp-schedule by @jopperm in #4525
• [Scheduling] Rewrite tests in SSP IR by @jopperm in #4523
• [Scheduling] Rewrite tests for OR-Tools-based schedulers in SSP IR by @jopperm in #4524
• [NFC] Document verilog baseline assumed for consuming tools by @darthscsi in #4575
• [Scheduling] Purge test passes. by @jopperm in #4572
• [firtool] Add --include-dir option, -I as alias. by @dtzSiFive in #4576
• [CI] Bump integration test images. by @jopperm in #4571
• [ExportVerilog] Move local name legalization to pre-pass by @uenoku in #4573
• [LowerTypes] Fix a race condition by @uenoku in #4582

Full Changelog: firtool-1.27.0...firtool-1.28.0

Firtool Release 1.27.0

Summary

• Now users can specify an include path to firtool using -I<directory>. FIRRTL will use this path to locate sources when loading files or reporting errors.

What's Changed

• [FIRRTL][CheckCombLoops] Reformat the lit tests. NFC by @prithayan in #4527
• [FIRRTL][CheckCombLoops] Handle scalar to Aggregate paths by @prithayan in #4526
• [Handshake] Fix iteration-over-modified-range bug in ControlMergeOp canonicalizer by @mortbopet in #4531
• [PyCDE] Separate BitVectors into Integers vs. Bits by @teqdruid in #4530
• [firtool] Add include directory flag by @dtzSiFive in #4539

Full Changelog: firtool-1.26.0...firtool-1.27.0

Firtool Release 1.26.0

Summary

• The tag name is renamed from sifive/ to firtool-
• Improved analog connection lowering
• A new combinatorial logic loop detection pass was merged
• Mux pragmas are stripped by default
• Extra guards to header macros
• SymbolDCE is moved to the later pipeline
• Bug fixes (IMCP invalid flow creation, ETC creates null operands)
• More aggregate preservation work

What's Changed

• Correct typos in ExpandWhens.cpp by @SpriteOvO in #4361
• [LowerXMR] Emit hierpathop's as private, so they can be removed if unused by @dtzSiFive in #4461
• [Scheduling] Overhaul simplex-based modulo scheduler. by @jopperm in #4426
• LLVM Bump by @nandor in #4463
• [LLHD] Install llhd-sim utility ### (when enabled). by @dtzSiFive in #4464
• [LowerToHW] Lower aggregate constant by @uenoku in #4451
• Revert "[LowerToHW] Lower aggregate constant" by @uenoku in #4465
• [FIRRTL] Simplify internal Analog connections by @tymcauley in #4466
• [FIRRTL] Fix InstanceOp Unknown Attribute Copying by @seldridge in #4468
• [CI] uploadBinaries.yml: Temporarily change 20.04 compiler to 12. by @dtzSiFive in #4475
• [CI] uploadBinaries: allow workflow_dispatch, test what we publish, drop cache by @dtzSiFive in #4474
• [NFC] small touchups before LLVM bump by @dtzSiFive in #4476
• [LowerToHW] Add extra guards to header macros by @uenoku in #4469
• [StandardToHandshake] Remove intermediate conversion ops by @RamirezLucas in #4480
• LLVM bump: move almost entirely to std::optional, fixes by @dtzSiFive in #4470
• [LowerSeqToSV] Initialize register element individually by @uenoku in #4478
• [ExportVerilog] Regard dead expressions as inlinable by @uenoku in #4486
• [SV] Mark SampledOp Pure by @uenoku in #4487
• [Seq] Create new clock enabled register op by @teqdruid in #4495
• [llvm] Bump LLVM to latest by @seldridge in #4491
• [PrepareForEmission] Handle twoState flags in variadic op lowerings by @uenoku in #4490
• [PyCDE] Improve Reg construct by @teqdruid in #4497
• [Pipeline] Add linear pipeline scheduling pass by @mortbopet in #4216
• [firtool] Strip mux pragmas by default, NFC by @uenoku in #4501
• [FIRRTL] remove GrandCentralSignalMapping pass + tests. by @dtzSiFive in #4505
• [firtool] Run SymbolDCE as late as possible. by @mikeurbach in #4504
• [FIRRTL] Handle Nodes in getDeclName. NFC. by @prithayan in #4512
• [FIRRTL][CheckCombCycles] Add a new pass to check for comb loops by @prithayan in #4368
• Bump LLVM by @youngar in #4511
• [LowerTypes] Force type lowering of ref type operations to fix memtap type mismatch by @uenoku in #4509
• [ExportVerilog] Inline bitcast op when only used by concat by @uenoku in #4493
• [Seq] Replace unitialized array elements of firreg with constant zero by @uenoku in #4510
• [CI] Enable statistics when building binaries for releases. by @dtzSiFive in #4515
• [FIRRTL][CheckCombLoops] Fix performance regression. by @prithayan in #4521
• [FIRRTL][CheckCombLoops] Switch to the new pass checkCombLoops instead of checkCombCycles by @prithayan in #4513

New Contributors

• @SpriteOvO made their first contribution in #4361

Full Changelog: sifive/1/25/0...firtool-1.26.0