Add baseline tests for some optimization handling

llvm · Aug 14, 2024 · 32ee4c9 · 32ee4c9
1 parent bab0408
commit 32ee4c9
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Showing 2 changed files with 84 additions and 0 deletions.
diff --git a/llvm/test/Transforms/InstCombine/loadstore-metadata.ll b/llvm/test/Transforms/InstCombine/loadstore-metadata.ll
@@ -173,6 +173,19 @@ define i32 @test_load_cast_combine_noundef(ptr %ptr) {
   ret i32 %c
 }
 
+define i32 @test_load_cast_combine_noalias_addrspace(ptr %ptr) {
+; Ensure (cast (load (...))) -> (load (cast (...))) preserves TBAA.
+; CHECK-LABEL: @test_load_cast_combine_noalias_addrspace(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[L1:%.*]] = load i32, ptr [[PTR:%.*]], align 4
+; CHECK-NEXT:    ret i32 [[L1]]
+;
+entry:
+  %l = load float, ptr %ptr, align 4, !noalias.addrspace !11
+  %c = bitcast float %l to i32
+  ret i32 %c
+}
+
 !0 = !{!1, !1, i64 0}
 !1 = !{!"scalar type", !2}
 !2 = !{!"root"}
@@ -184,3 +197,4 @@ define i32 @test_load_cast_combine_noundef(ptr %ptr) {
 !8 = !{i32 1}
 !9 = !{i64 8}
 !10 = distinct !{}
+!11 = !{i32 5, i32 6}
diff --git a/llvm/test/Transforms/SimplifyCFG/hoist-with-metadata.ll b/llvm/test/Transforms/SimplifyCFG/hoist-with-metadata.ll
@@ -316,10 +316,80 @@ out:
   ret void
 }
 
+define void @hoist_noalias_addrspace_both(i1 %c, ptr %p, i64 %val) {
+; CHECK-LABEL: @hoist_noalias_addrspace_both(
+; CHECK-NEXT:  if:
+; CHECK-NEXT:    [[T:%.*]] = atomicrmw add ptr [[P:%.*]], i64 [[VAL:%.*]] seq_cst, align 8
+; CHECK-NEXT:    ret void
+;
+if:
+  br i1 %c, label %then, label %else
+
+then:
+  %t = atomicrmw add ptr %p, i64 %val seq_cst, !noalias.addrspace !4
+  br label %out
+
+else:
+  %e = atomicrmw add ptr %p, i64 %val seq_cst, !noalias.addrspace !4
+  br label %out
+
+out:
+  ret void
+}
+
+define void @hoist_noalias_addrspace_one(i1 %c, ptr %p, i64 %val) {
+; CHECK-LABEL: @hoist_noalias_addrspace_one(
+; CHECK-NEXT:  if:
+; CHECK-NEXT:    [[T:%.*]] = atomicrmw add ptr [[P:%.*]], i64 [[VAL:%.*]] seq_cst, align 8
+; CHECK-NEXT:    ret void
+;
+if:
+  br i1 %c, label %then, label %else
+
+then:
+  %t = atomicrmw add ptr %p, i64 %val seq_cst, !noalias.addrspace !4
+  br label %out
+
+else:
+  %e = atomicrmw add ptr %p, i64 %val seq_cst
+  br label %out
+
+out:
+  ret void
+}
+
+define void @hoist_noalias_addrspace_switch(i64 %i, ptr %p, i64 %val) {
+; CHECK-LABEL: @hoist_noalias_addrspace_switch(
+; CHECK-NEXT:  out:
+; CHECK-NEXT:    [[T:%.*]] = atomicrmw add ptr [[P:%.*]], i64 [[VAL:%.*]] seq_cst, align 8
+; CHECK-NEXT:    ret void
+;
+  switch i64 %i, label %bb0 [
+  i64 1, label %bb1
+  i64 2, label %bb2
+  ]
+bb0:
+  %t = atomicrmw add ptr %p, i64 %val seq_cst, !noalias.addrspace !4
+  br label %out
+bb1:
+  %e = atomicrmw add ptr %p, i64 %val seq_cst, !noalias.addrspace !5
+  br label %out
+bb2:
+  %f = atomicrmw add ptr %p, i64 %val seq_cst, !noalias.addrspace !6
+  br label %out
+out:
+  ret void
+}
+
+
 !0 = !{ i8 0, i8 1 }
 !1 = !{ i8 3, i8 5 }
 !2 = !{}
 !3 = !{ i8 7, i8 9 }
+!4 = !{i32 5, i32 6}
+!5 = !{i32 5, i32 7}
+!6 = !{i32 4, i32 8}
+
 ;.
 ; CHECK: [[RNG0]] = !{i8 0, i8 1, i8 3, i8 5}
 ; CHECK: [[RNG1]] = !{i8 0, i8 1, i8 3, i8 5, i8 7, i8 9}