Bump vtr-verilog-to-routing from `04959b7` to `8178b71` #2859

	name: Code Format

	# Run CI on push, PR, and weekly.

	on:
	workflow_dispatch:
	pull_request:
	push:
	branches:
	- 'master'
	schedule:
	- cron: "0 0 * * 0 " # weekly

	concurrency:
	group: ${{ github.workflow }}-${{ github.ref }}
	cancel-in-progress: true

	# Multiple job to tests
	jobs:
	change_detect:
	name: "Check"
	runs-on: ubuntu-22.04
	strategy:
	fail-fast: false
	matrix:
	config:
	- name: "C/C++"
	code_type: "-cpp"
	dependency_version: "ubuntu22p04"
	- name: "XML"
	code_type: "-xml"
	dependency_version: "ubuntu22p04"
	- name: "Python"
	code_type: "-py"
	dependency_version: "ubuntu22p04"
	steps:
	- name: Cancel previous
	uses: styfle/cancel-workflow-action@0.12.1
	with:
	access_token: ${{ github.token }}

	- name: Checkout OpenFPGA repo
	uses: actions/checkout@v2

	- name: Install dependencies
	run: \|
	sudo bash ./.github/workflows/install_dependencies_build_${{ matrix.config.dependency_version }}.sh
	sudo python3 -m pip install -r requirements.txt

	- name: Dump tool versions
	run: \|
	clang-format-14 --version
	black --version

	- name: Check format
	run: ./dev/check-format.sh ${{ matrix.config.code_type }}

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