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[test] update golden
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@tangxifan
tangxifan committed Nov 14, 2024
1 parent e863333 commit d264b39
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Showing 24 changed files with 1,179 additions and 1,117 deletions.
4 changes: 2 additions & 2 deletions ...c_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
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Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb;
initial begin
clk[0] <= 1'b0;
while(1) begin
#0.809066534
#0.4880859554
clk[0] <= !clk[0];
end
end
Expand Down Expand Up @@ -106,7 +106,7 @@ initial begin
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
#11.32693195
#6.833203316
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
Expand Down
77 changes: 56 additions & 21 deletions ...ic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
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Large diffs are not rendered by default.

50 changes: 25 additions & 25 deletions ...ests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v
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Original file line number Diff line number Diff line change
Expand Up @@ -45,12 +45,11 @@ wire [0:0] clk_fm;
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[14] -----
assign gfpga_pad_GPIO_PAD_fm[14] = b[0];

// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
assign c[0] = gfpga_pad_GPIO_PAD_fm[12];
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[1] -----
assign c[0] = gfpga_pad_GPIO_PAD_fm[1];

// ----- Wire unused FPGA I/Os to constants -----
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[1] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[2] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[3] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[4] = 1'b0;
Expand All @@ -60,6 +59,7 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
Expand Down Expand Up @@ -132,8 +132,8 @@ initial begin
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
Expand All @@ -154,8 +154,8 @@ initial begin
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
Expand Down Expand Up @@ -238,12 +238,12 @@ initial begin
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}};
Expand Down Expand Up @@ -288,12 +288,12 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}};
Expand All @@ -302,12 +302,12 @@ initial begin
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
Expand Down Expand Up @@ -382,8 +382,8 @@ initial begin
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
Expand Down Expand Up @@ -426,8 +426,8 @@ initial begin
force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = 3'b001;
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = 3'b110;
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
Expand Down Expand Up @@ -474,8 +474,8 @@ initial begin
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101;
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010;
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}};
Expand Down
30 changes: 15 additions & 15 deletions ...ks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit
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Original file line number Diff line number Diff line change
Expand Up @@ -155,9 +155,7 @@
0
0
0
1
0
1
0
0
0
Expand Down Expand Up @@ -199,6 +197,10 @@
0
0
0
1
0
0
0
0
0
0
Expand All @@ -222,8 +224,6 @@
0
0
0
1
1
0
0
1
Expand Down Expand Up @@ -301,12 +301,12 @@
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
Expand Down Expand Up @@ -360,12 +360,12 @@
1
1
1
0
1
1
1
1
1
0
1
1
1
Expand Down Expand Up @@ -459,11 +459,11 @@
0
0
0
1
0
0
0
1
0
0
0
0
0
Expand All @@ -472,12 +472,12 @@
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
Expand Down
34 changes: 17 additions & 17 deletions ...ks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -314,11 +314,11 @@
</bit>
<bit id="373" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_5.mem_out[0]">
</bit>
<bit id="372" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[2]">
<bit id="372" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[2]">
</bit>
<bit id="371" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[1]">
</bit>
<bit id="370" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]">
<bit id="370" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]">
</bit>
<bit id="369" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[2]">
</bit>
Expand Down Expand Up @@ -398,7 +398,7 @@
</bit>
<bit id="331" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_2.mem_out[0]">
</bit>
<bit id="330" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[2]">
<bit id="330" value="1" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[2]">
</bit>
<bit id="329" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_1.mem_out[1]">
</bit>
Expand Down Expand Up @@ -448,9 +448,9 @@
</bit>
<bit id="306" value="0" path="fpga_top.sb_1__1_.mem_left_track_9.mem_out[0]">
</bit>
<bit id="305" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
<bit id="305" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
</bit>
<bit id="304" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
<bit id="304" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
</bit>
<bit id="303" value="0" path="fpga_top.sb_1__1_.mem_left_track_5.mem_out[1]">
</bit>
Expand Down Expand Up @@ -606,17 +606,17 @@
</bit>
<bit id="227" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_23.mem_out[0]">
</bit>
<bit id="226" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[1]">
<bit id="226" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[1]">
</bit>
<bit id="225" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[0]">
<bit id="225" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_21.mem_out[0]">
</bit>
<bit id="224" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[1]">
</bit>
<bit id="223" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[0]">
</bit>
<bit id="222" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]">
<bit id="222" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]">
</bit>
<bit id="221" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]">
<bit id="221" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]">
</bit>
<bit id="220" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_15.mem_out[2]">
</bit>
Expand Down Expand Up @@ -724,7 +724,7 @@
</bit>
<bit id="168" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
<bit id="167" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
<bit id="167" value="0" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
<bit id="166" value="1" path="fpga_top.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
Expand All @@ -734,7 +734,7 @@
</bit>
<bit id="163" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
<bit id="162" value="0" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
<bit id="162" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
<bit id="161" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit>
Expand Down Expand Up @@ -922,15 +922,15 @@
</bit>
<bit id="69" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[1]">
</bit>
<bit id="68" value="1" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]">
<bit id="68" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]">
</bit>
<bit id="67" value="0" path="fpga_top.sb_1__0_.mem_top_track_6.mem_out[1]">
</bit>
<bit id="66" value="0" path="fpga_top.sb_1__0_.mem_top_track_6.mem_out[0]">
</bit>
<bit id="65" value="0" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[1]">
</bit>
<bit id="64" value="1" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
<bit id="64" value="0" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
</bit>
<bit id="63" value="0" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[2]">
</bit>
Expand All @@ -948,17 +948,17 @@
</bit>
<bit id="56" value="0" path="fpga_top.sb_0__0_.mem_right_track_24.mem_out[0]">
</bit>
<bit id="55" value="1" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[1]">
<bit id="55" value="0" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[1]">
</bit>
<bit id="54" value="1" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[0]">
<bit id="54" value="0" path="fpga_top.sb_0__0_.mem_right_track_22.mem_out[0]">
</bit>
<bit id="53" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[1]">
</bit>
<bit id="52" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[0]">
</bit>
<bit id="51" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]">
<bit id="51" value="0" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]">
</bit>
<bit id="50" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]">
<bit id="50" value="0" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]">
</bit>
<bit id="49" value="0" path="fpga_top.sb_0__0_.mem_right_track_16.mem_out[1]">
</bit>
Expand Down
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