Support intermediate drivers in programmable clock network

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• Internal drivers can only engage clock network at switching points. As a result, internal driver may only be propagated a small portion of FPGA fabric. Otherwise, at least 3 layers are required.

What does this pull request change?

This PR improves in the following aspects:

• Introduce new syntax to support internal drivers occur at any intermediate stops on a clock spine. See the figure below for an illustrative example.

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.