top/*/dbe_bpm_gen: change aux_clk input to RF/8 = 62.5MHz

lnls-dig · Jul 13, 2020 · e037a0b · e037a0b
1 parent 99d3435
commit e037a0b
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd b/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
@@ -1561,13 +1561,13 @@ begin
    -- Auxiliary clock
   cmp_aux_sys_pll_inst : sys_pll
   generic map (
-    -- RF*5/36 ~ 69.44 MHz input clock ~ 14.4 ns
-    g_clkin_period                          => 14.400,
+    -- RF/8 ~ 62.500 input clock ~ 16 ns
+    g_clkin_period                          => 16.000,
     g_divclk_divide                         => 1,
-    g_clkbout_mult_f                        => 18,
+    g_clkbout_mult_f                        => 16,
 
     -- 125 MHz output clock
-    g_clk0_divide_f                         => 10
+    g_clk0_divide_f                         => 8
   )
   port map (
     rst_i                                   => '0',