Merge branch 'devel'

.gitmodules

@@ -7,3 +7,12 @@
 [submodule "hdl/ip_cores/infra-cores"]
 	path = hdl/ip_cores/infra-cores
 	url = https://github.com/lnls-dig/infra-cores
+[submodule "hdl/ip_cores/afc-gw"]
+	path = hdl/ip_cores/afc-gw
+	url = https://github.com/lnls-dig/afc-gw
+[submodule "hdl/ip_cores/CommsCtrlFPGA"]
+	path = hdl/ip_cores/CommsCtrlFPGA
+	url = https://github.com/lnls-dig/CommsCtrlFPGA
+[submodule "hdl/ip_cores/fofb-ctrl-gw"]
+	path = hdl/ip_cores/fofb-ctrl-gw
+	url = https://github.com/lnls-dig/fofb-ctrl-gw

hdl/Manifest.py

@@ -5,5 +5,8 @@
                 "ip_cores/general-cores",
                 "ip_cores/dsp-cores",
                 "ip_cores/infra-cores",
+                "ip_cores/afc-gw",
+                "ip_cores/CommsCtrlFPGA",
+                "ip_cores/fofb-ctrl-gw",
             ]
     };

hdl/modules/wb_orbit_intlk/orbit_intlk_ang.vhd

@@ -502,6 +502,7 @@ begin
 
   ang_intlk_bigger <= ang_intlk_bigger_or(c_INTLK_GEN_UPTO_CHANNEL+1);
   intlk_ang_bigger_o  <= ang_intlk_bigger;
+  intlk_ang_bigger_any_o  <= ang_intlk_bigger;
 
   ang_intlk_bigger_ltc_or(0) <= '0';
   -- ORing all ang_bigger_ltc
@@ -523,6 +524,7 @@ begin
 
   ang_intlk_smaller <= ang_intlk_smaller_or(c_INTLK_GEN_UPTO_CHANNEL+1);
   intlk_ang_smaller_o  <= ang_intlk_smaller;
+  intlk_ang_smaller_any_o  <= ang_intlk_smaller;
 
   ang_intlk_smaller_ltc_or(0) <= '0';
   -- ORing all ang_smaller_ltc

hdl/modules/wb_orbit_intlk/orbit_intlk_trans.vhd

@@ -499,6 +499,7 @@ begin
 
   trans_intlk_bigger <= trans_intlk_bigger_or(c_INTLK_GEN_UPTO_CHANNEL+1);
   intlk_trans_bigger_o  <= trans_intlk_bigger;
+  intlk_trans_bigger_any_o  <= trans_intlk_bigger;
 
   trans_intlk_bigger_ltc_or(0) <= '0';
   -- ORing all trans_bigger_ltc
@@ -520,6 +521,7 @@ begin
 
   trans_intlk_smaller <= trans_intlk_smaller_or(c_INTLK_GEN_UPTO_CHANNEL+1);
   intlk_trans_smaller_o  <= trans_intlk_smaller;
+  intlk_trans_smaller_any_o  <= trans_intlk_smaller;
 
   trans_intlk_smaller_ltc_or(0) <= '0';
   -- ORing all trans_smaller_ltc

hdl/syn/.gitignore

@@ -90,4 +90,5 @@ planAhead_run_*/
 *synthesize.tcl
 *translate.tcl
 *project.tcl
+*synthesis_descriptor_pkg.vhd
 *files.tcl

hdl/syn/afc_v3/vivado/dbe_bpm2_bo_sirius/Manifest.py → hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py

@@ -3,6 +3,11 @@
 
 language = "vhdl"
 
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+    fetchto = "../../ip_cores"
+
 syn_device = "xc7a200t"
 syn_grade = "-2"
 syn_package = "ffg1156"
@@ -23,6 +28,11 @@
     ["steps.post_route_phys_opt_design.is_enabled", "1"],
     ["steps.write_bitstream.args.verbose", "1"]]
 
+board = "afc"
+
+# For appending the afc_ref_design.xdc to synthesis
+afc_base_xdc = ['acq']
+
 import os
 import sys
 if os.path.isfile("synthesis_descriptor_pkg.vhd"):
@@ -32,4 +42,19 @@
 
 machine_pkg = "sirius_bo_250M";
 
-modules = { "local" : [ "../../../../top/afc_v3/vivado/dbe_bpm2" ] };
+# Pass more XDC to afc-gw so it will merge it last with
+# other .xdc. We need this as we depend on variables defined
+# on afc_base xdc files.
+xdc_files = [
+    "../dbe_common/dbe_bpm2.xdc",
+]
+
+additional_xdc = []
+for f in xdc_files:
+    additional_xdc.append(os.path.abspath(f))
+
+modules = {
+    "local" : [
+        "../../../top/afc_v3/dbe_bpm2"
+    ]
+}

hdl/syn/afc_v3/vivado/dbe_bpm2_bo_sirius/build_synthesis_sdb.sh → hdl/syn/afc_v3/dbe_bpm2_bo_sirius/build_synthesis_sdb.sh

@@ -10,7 +10,7 @@ SYNTH_INFO_PROJECT="bpm-gw-bo-sirius"
 SYNTH_INFO_TOOL="VIVADO"
 SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)
 
-SYNTH_INFO_COMMAND="../../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}"
+SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}"
 
 # Generate synthesis file
 echo $SYNTH_INFO_COMMAND

hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py

@@ -0,0 +1,61 @@
+target = "xilinx"
+action = "synthesis"
+
+language = "vhdl"
+
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+    fetchto = "../../ip_cores"
+
+syn_device = "xc7a200t"
+syn_grade = "-2"
+syn_package = "ffg1156"
+syn_top = "dbe_bpm2_with_dcc"
+syn_project = "dbe_bpm2_with_dcc"
+syn_tool = "vivado"
+syn_properties = [
+    ["steps.synth_design.args.more options", "-verbose"],
+    ["steps.synth_design.args.retiming", "1"],
+    ["steps.synth_design.args.assert", "1"],
+    ["steps.opt_design.args.verbose", "1"],
+    ["steps.opt_design.is_enabled", "1"],
+    ["steps.phys_opt_design.args.directive", "Explore"],
+    ["steps.phys_opt_design.args.more options", "-verbose"],
+    ["steps.phys_opt_design.is_enabled", "1"],
+    ["steps.post_route_phys_opt_design.args.directive", "Explore"],
+    ["steps.post_route_phys_opt_design.args.more options", "-verbose"],
+    ["steps.post_route_phys_opt_design.is_enabled", "1"],
+    ["steps.write_bitstream.args.verbose", "1"]]
+
+board = "afc"
+
+# For appending the afc_ref_design.xdc to synthesis
+afc_base_xdc = ['acq']
+
+import os
+import sys
+if os.path.isfile("synthesis_descriptor_pkg.vhd"):
+    files = ["synthesis_descriptor_pkg.vhd"];
+else:
+    sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)")
+
+machine_pkg = "sirius_bo_250M";
+
+# Pass more XDC to afc-gw so it will merge it last with
+# other .xdc. We need this as we depend on variables defined
+# on afc_base xdc files.
+xdc_files = [
+    "../dbe_common/dbe_bpm2.xdc",
+    "../dbe_common/afc_p2p_gts.xdc",
+]
+
+additional_xdc = []
+for f in xdc_files:
+    additional_xdc.append(os.path.abspath(f))
+
+modules = {
+    "local" : [
+        "../../../top/afc_v3/dbe_bpm2_with_dcc"
+    ]
+}

hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/build_synthesis_sdb.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+# Exit on error
+set -e
+# Check for uninitialized variables
+set -u
+
+# Maximum of 16 chars
+SYNTH_INFO_PROJECT="bpm-gw-bo-sirius"
+SYNTH_INFO_TOOL="VIVADO"
+SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)
+
+SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}"
+
+# Generate synthesis file
+echo $SYNTH_INFO_COMMAND
+eval $SYNTH_INFO_COMMAND

hdl/syn/afc_v3/vivado/dbe_bpm2_sr_sirius/Manifest.py → hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py

@@ -3,6 +3,11 @@
 
 language = "vhdl"
 
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+    fetchto = "../../ip_cores"
+
 syn_device = "xc7a200t"
 syn_grade = "-2"
 syn_package = "ffg1156"
@@ -23,6 +28,11 @@
     ["steps.post_route_phys_opt_design.is_enabled", "1"],
     ["steps.write_bitstream.args.verbose", "1"]]
 
+board = "afc"
+
+# For appending the afc_ref_design.xdc to synthesis
+afc_base_xdc = ['acq']
+
 import os
 import sys
 if os.path.isfile("synthesis_descriptor_pkg.vhd"):
@@ -32,4 +42,19 @@
 
 machine_pkg = "sirius_sr_250M";
 
-modules = { "local" : [ "../../../../top/afc_v3/vivado/dbe_bpm2" ] };
+# Pass more XDC to afc-gw so it will merge it last with
+# other .xdc. We need this as we depend on variables defined
+# on afc_base xdc files.
+xdc_files = [
+    "../dbe_common/dbe_bpm2.xdc",
+]
+
+additional_xdc = []
+for f in xdc_files:
+    additional_xdc.append(os.path.abspath(f))
+
+modules = {
+    "local" : [
+        "../../../top/afc_v3/dbe_bpm2"
+    ]
+}

hdl/syn/afc_v3/vivado/dbe_bpm2_sr_sirius/build_synthesis_sdb.sh → hdl/syn/afc_v3/dbe_bpm2_sr_sirius/build_synthesis_sdb.sh

@@ -10,7 +10,7 @@ SYNTH_INFO_PROJECT="bpm-gw-sr-sirius"
 SYNTH_INFO_TOOL="VIVADO"
 SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)
 
-SYNTH_INFO_COMMAND="../../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}"
+SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}"
 
 # Generate synthesis file
 echo $SYNTH_INFO_COMMAND

hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py

@@ -0,0 +1,61 @@
+target = "xilinx"
+action = "synthesis"
+
+language = "vhdl"
+
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+    fetchto = "../../ip_cores"
+
+syn_device = "xc7a200t"
+syn_grade = "-2"
+syn_package = "ffg1156"
+syn_top = "dbe_bpm2_with_dcc"
+syn_project = "dbe_bpm2_with_dcc"
+syn_tool = "vivado"
+syn_properties = [
+    ["steps.synth_design.args.more options", "-verbose"],
+    ["steps.synth_design.args.retiming", "1"],
+    ["steps.synth_design.args.assert", "1"],
+    ["steps.opt_design.args.verbose", "1"],
+    ["steps.opt_design.is_enabled", "1"],
+    ["steps.phys_opt_design.args.directive", "Explore"],
+    ["steps.phys_opt_design.args.more options", "-verbose"],
+    ["steps.phys_opt_design.is_enabled", "1"],
+    ["steps.post_route_phys_opt_design.args.directive", "Explore"],
+    ["steps.post_route_phys_opt_design.args.more options", "-verbose"],
+    ["steps.post_route_phys_opt_design.is_enabled", "1"],
+    ["steps.write_bitstream.args.verbose", "1"]]
+
+board = "afc"
+
+# For appending the afc_ref_design.xdc to synthesis
+afc_base_xdc = ['acq']
+
+import os
+import sys
+if os.path.isfile("synthesis_descriptor_pkg.vhd"):
+    files = ["synthesis_descriptor_pkg.vhd"];
+else:
+    sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)")
+
+machine_pkg = "sirius_sr_250M";
+
+# Pass more XDC to afc-gw so it will merge it last with
+# other .xdc. We need this as we depend on variables defined
+# on afc_base xdc files.
+xdc_files = [
+    "../dbe_common/dbe_bpm2.xdc",
+    "../dbe_common/afc_p2p_gts.xdc",
+]
+
+additional_xdc = []
+for f in xdc_files:
+    additional_xdc.append(os.path.abspath(f))
+
+modules = {
+    "local" : [
+        "../../../top/afc_v3/dbe_bpm2_with_dcc"
+    ]
+}

hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_bitstream_local.sh

@@ -0,0 +1,11 @@
+#!/bin/bash
+
+# Exit on error
+set -e
+# Check for uninitialized variables
+set -u
+
+COMMAND="(./build_synthesis_sdb.sh; hdlmake -a makefile; time make; date) 2>&1 | tee make_output"
+
+echo $COMMAND
+eval $COMMAND

hdl/syn/afc_v1/dbe_bpm/build_bitstream_remote.sh → hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_bitstream_remote.sh

@@ -1,5 +1,10 @@
 #!/bin/bash
 
+# Exit on error
+set -e
+# Check for uninitialized variables
+set -u
+
 COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &"
 
 echo $COMMAND

hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_synthesis_sdb.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+# Exit on error
+set -e
+# Check for uninitialized variables
+set -u
+
+# Maximum of 16 chars
+SYNTH_INFO_PROJECT="bpm-gw-sr-sirius"
+SYNTH_INFO_TOOL="VIVADO"
+SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)
+
+SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}"
+
+# Generate synthesis file
+echo $SYNTH_INFO_COMMAND
+eval $SYNTH_INFO_COMMAND

hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/synthesis_descriptor_pkg.vhd

@@ -0,0 +1,6 @@
+-- This file will be overwritten prior to synthesis,
+-- by hdlmake "syn_pre_cmd" specified on top Manifest.py.
+--
+-- However, hdlmake requires all files to be present
+-- on parsing-time. So, fool the tool with this dummy
+-- file so we can bypass this requirement.