Merge branch 'devel'

lnls-dig · May 6, 2019 · 6128ee0 · 6128ee0
2 parents 95d7288 + 3438ad8
commit 6128ee0
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Showing 3 changed files with 103 additions and 15 deletions.
diff --git a/hdl/modules/cic/cic_dyn.vhd b/hdl/modules/cic/cic_dyn.vhd
@@ -210,7 +210,7 @@ begin  -- architecture str
                 data_mask_pt_counter <= to_unsigned(0, data_mask_pt_counter'length);
                 data_mask_end_counter <= to_unsigned(0, data_mask_end_counter'length);
                 -- wait for tag transition
-                if data_tag_change = '1' then
+                if decimation_strobe = '1' then
                   -- mask input samples up to a max
                   if valid_i = '1' then
 
@@ -252,7 +252,7 @@ begin  -- architecture str
 
                     -- No time to check the transition at the CHECK_TRANSITION
                     -- state. Change now
-                    if data_tag_change = '1' and valid_i = '1' then
+                    if decimation_strobe = '1' and valid_i = '1' then
                       if data_mask_beg_bypass = '0' then
                         data_d0 <= (others => '0');
                         fsm_data_mask_current_state <= MASKING_BEG;
@@ -289,7 +289,7 @@ begin  -- architecture str
 
                     -- No time to check the transition at the CHECK_TRANSITION
                     -- state. Change now
-                    if data_tag_change = '1' and valid_i = '1' then
+                    if decimation_strobe = '1' and valid_i = '1' then
                       if data_mask_beg_bypass = '0' then
                         data_d0 <= (others => '0');
                         fsm_data_mask_current_state <= MASKING_BEG;
@@ -322,7 +322,7 @@ begin  -- architecture str
 
                   -- No time to check the transition at the CHECK_TRANSITION
                   -- state. Change now
-                  if data_tag_change = '1' and valid_i = '1' then
+                  if decimation_strobe = '1' and valid_i = '1' then
                     if data_mask_beg_bypass = '0' then
                       data_d0 <= (others => '0');
                       fsm_data_mask_current_state <= MASKING_BEG;

diff --git a/hdl/modules/dsp_cores_pkg.vhd b/hdl/modules/dsp_cores_pkg.vhd
@@ -858,6 +858,70 @@ package dsp_cores_pkg is
       monit_pos_ce_o     : out std_logic);
   end component position_calc;
 
+  component swap_freqgen
+  generic(
+    g_delay_vec_width                       : natural := 8;
+    g_swap_div_freq_vec_width               : natural := 16
+  );
+  port(
+    clk_i                                   : in  std_logic;
+    rst_n_i                                 : in  std_logic;
+
+    sync_trig_i                             : in  std_logic;
+
+    -- Swap and de-swap signals
+    swap_o                                  : out std_logic;
+    deswap_o                                : out std_logic;
+
+    -- Swap mode setting
+    swap_mode_i                             : in  t_swap_mode;
+
+    -- Swap frequency settings
+    swap_div_f_i                            : in  std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
+
+    -- De-swap delay setting
+    deswap_delay_i                          : in  std_logic_vector(g_delay_vec_width-1 downto 0)
+  );
+  end component;
+
+  component deswap_channels
+  generic(
+    g_ch_width  : natural := 16
+  );
+  port(
+    clk_i       : in   std_logic;
+    rst_n_i     : in   std_logic;
+
+    deswap_i    : in   std_logic;
+
+    ch1_i       : in   std_logic_vector(g_ch_width-1 downto 0);
+    ch2_i       : in   std_logic_vector(g_ch_width-1 downto 0);
+    ch_valid_i  : in   std_logic;
+
+    ch1_o       : out  std_logic_vector(g_ch_width-1 downto 0);
+    ch2_o       : out  std_logic_vector(g_ch_width-1 downto 0);
+    deswap_o    : out std_logic;
+    ch_valid_o  : out  std_logic
+  );
+  end component;
+
+  component swmode_sel
+  port(
+    clk_i                                     :    in  std_logic;
+    rst_n_i                                   :    in  std_logic;
+
+    -- Swap master clock
+    clk_swap_i                                :    in  std_logic;
+
+    -- Swap and de-swap signals
+    swap_o                                    :    out std_logic;
+    deswap_o                                  :    out std_logic;
+
+    -- Swap mode setting
+    swap_mode_i                               :    in  t_swap_mode
+  );
+  end component;
+
   component bpm_swap
     generic(
       g_delay_vec_width         : natural := 8;

diff --git a/hdl/modules/wb_position_calc/wb_position_calc_core.vhd b/hdl/modules/wb_position_calc/wb_position_calc_core.vhd
@@ -287,6 +287,20 @@ end wb_position_calc_core;
 
 architecture rtl of wb_position_calc_core is
 
+  ---------------------------------------------------------
+  --                     Functions                       --
+  ---------------------------------------------------------
+
+  function f_log2_size (A : natural) return natural is
+  begin
+    for I in 1 to 64 loop               -- Works for up to 64 bits
+      if (2**I >= A) then
+        return(I);
+      end if;
+    end loop;
+    return(63);
+  end f_log2_size;
+
   ---------------------------------------------------------
   --                     Constants                       --
   ---------------------------------------------------------
@@ -309,6 +323,8 @@ architecture rtl of wb_position_calc_core is
   constant c_tbt_cic_mask_samples_width     : natural := 10;
   constant c_fofb_cic_mask_samples_width    : natural := 16;
 
+  constant c_tbt_ratio_log2                 : natural := f_log2_size(g_tbt_ratio);
+
   constant c_k_width                        : natural := 24;
 
   constant c_cnt_width_raw                  : natural := g_adc_ratio;
@@ -1075,22 +1091,30 @@ begin
   fofb_decim_mask_num_samples               <= unsigned(regs_out.sw_data_mask_samples_o);
 
   -- Generate proper tag for TBT
-  cmp_tbt_trigger2tag : trigger2tag
+  cmp_tbt_tag : swap_freqgen
   generic map (
-    g_delay_width                            => c_tbt_decim_tag_dly_width,
-    g_tag_size                               => 1
+    g_delay_vec_width                       => c_tbt_decim_tag_dly_width,
+    g_swap_div_freq_vec_width               => c_tbt_ratio_log2
   )
   port map (
-    fs_clk_i                                 => fs_clk_i,
-    fs_rst_n_i                               => fs_rst_n_i,
+    clk_i                                   => fs_clk_i,
+    rst_n_i                                 => fs_rst_n_i,
+
+    sync_trig_i                             => sync_tbt_trig_i,
+
+    -- Swap and de-swap signals
+    swap_o                                  => open,
+    deswap_o                                => tbt_decim_tag_logic,
+
+    -- Swap mode setting
+    swap_mode_i                             => c_swmode_swap_deswap,
 
-    -- Pulse programmable delay
-    pulse_dly_i                              => tbt_decim_tag_dly_c,
-    -- Pulse input
-    pulse_i                                  => sync_tbt_trig_i,
+    -- Swap frequency settings
+    swap_div_f_i                            => std_logic_vector(to_unsigned(g_tbt_ratio,
+                                                                            c_tbt_ratio_log2)),
 
-    -- Output counter
-    tag_o                                    => tbt_decim_tag_logic
+    -- De-swap delay setting
+    deswap_delay_i                          => tbt_decim_tag_dly_c
   );
 
   tbt_decim_tag(0) <= tbt_decim_tag_logic;