testbench/cic: fix enable signal for freqgen submodules

lnls-dig · Jul 9, 2020 · c1928d5 · c1928d5
1 parent 19bd3f7
commit c1928d5
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/hdl/testbench/cic/wb_bpm_swap/bpm_swap/swap_freqgen.vhd b/hdl/testbench/cic/wb_bpm_swap/bpm_swap/swap_freqgen.vhd
@@ -89,7 +89,7 @@ begin
   port map (
     clk_i        =>  clk_i,
     rst_n_i      =>  rst_n_i,
-    en_i         =>  en_i,
+    en_i         =>  '1',
     clk_swap_i   =>  clk_swap,
     swap_mode_i  =>  swap_mode_i,
     swap_o       =>  swap_o,
@@ -102,7 +102,7 @@ begin
   )
   port map (
     clk_i   =>  clk_i,
-    en_i    =>  en_i,
+    en_i    =>  '1',
     d_i     =>  deswap,
     q_o     =>  deswap_o,
     a_i     =>  deswap_delay_i