testbench/cic: add fs timescale to simulation

lnls-dig · Jul 10, 2020 · c6c5a57 · c6c5a57
1 parent 4a58967
commit c6c5a57
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/hdl/testbench/cic/run.do b/hdl/testbench/cic/run.do
@@ -1,7 +1,8 @@
 vcom cic_bench.vhd
 -- make -f Makefile
 -- output log file to file "output.log", set simulation resolution to "fs"
-vsim -l output.log -t 1ps -L unisim work.cic_bench -voptargs="+acc"
+vsim -l output.log -voptargs="+acc" -t fs +notimingchecks -L unisim work.cic_bench
+
 set StdArithNoWarnings 1
 set NumericStdNoWarnings 1
 do wave.do