Merge branch 'devel'

hdl/modules/Manifest.py

@@ -23,5 +23,6 @@
             "clock_driver",
             "machine",
             "rp_math_pack",
-            "part_delta_sigma"
+            "part_delta_sigma",
+            "hpf_adcinput"
          ] };

hdl/modules/dsp_cores_pkg.vhd

@@ -1602,6 +1602,18 @@ package dsp_cores_pkg is
   );
   end component;
 
+  component hpf_adcinput
+  port
+  (
+    clk_i    : in  std_logic;
+    rst_n_i  : in  std_logic;
+    ce_i     : in  std_logic;
+
+    data_i   : in  std_logic_vector(15 downto 0);
+    data_o   : out std_logic_vector(15 downto 0)
+  );
+  end component hpf_adcinput;
+
 end dsp_cores_pkg;
 
 package body dsp_cores_pkg is

hdl/modules/hpf_adcinput/Manifest.py

@@ -0,0 +1,3 @@
+files = ["hpf_adcinput.vhd",
+         "mac1reg.vhd",
+         "mac2reg.vhd"]

hdl/modules/hpf_adcinput/hpf_adcinput.vhd

@@ -0,0 +1,142 @@
+------------------------------------------------------------------------------
+-- Title      : Systolic High Pass FIR Filter
+------------------------------------------------------------------------------
+-- Author     : Daniel Tavares
+-- Company    : CNPEM LNLS-DIG
+-- Created    : 2019-11-23
+-- Platform   : FPGA-generic
+-------------------------------------------------------------------------------
+-- Description: Systolic FIR for high pass filter.
+--              Coefficients are calculated to meet the specification:
+--                - Stopband norm. frequency: 0.04545
+--                - Passband norm. frequency: 0.4545
+--                - Attenuation at stopband: 60 dB
+--                - Attenuation ripple at passband: +/- 0.1 dB
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019 CNPEM
+-- Licensed under GNU Lesser General Public License (LGPL) v3.0
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author              Description
+-- 2019-11-23  1.0      daniel.tavares      Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_signed.all;
+
+entity hpf_adcinput is
+port
+(
+  clk_i   : in  std_logic;
+  rst_n_i : in  std_logic;
+  ce_i    : in  std_logic;
+  data_i  : in  std_logic_vector (15 downto 0);
+  data_o  : out std_logic_vector (15 downto 0)
+);
+end hpf_adcinput;
+
+architecture rtl of hpf_adcinput is
+
+  type t_coef is array(12 downto 0) of std_logic_vector(24 downto 0);
+  signal coef : t_coef;
+
+  type t_cascade is array(11 downto 0) of std_logic_vector(47 downto 0);
+  signal cascade : t_cascade;
+
+  type t_data_io is array(12 downto 0) of std_logic_vector(17 downto 0);
+  signal data : t_data_io;
+
+  signal data_full : std_logic_vector(47 downto 0);
+
+  component mac1reg is
+  port
+  (
+    clk_i  : in  std_logic;
+    data_i : in  std_logic_vector (17 downto 0);
+    coef_i : in  std_logic_vector (24 downto 0);
+    data_o : out std_logic_vector (17 downto 0);
+    mac_o :  out std_logic_vector (47 downto 0);
+    casc_o : out std_logic_vector (47 downto 0)
+  );
+  end component;
+
+  component mac2reg is
+  port
+  (
+    clk_i  : in  std_logic;
+    data_i : in  std_logic_vector (17 downto 0);
+    coef_i : in  std_logic_vector (24 downto 0);
+    casc_i : in  std_logic_vector (47 downto 0);
+    data_o : out std_logic_vector (17 downto 0);
+    mac_o :  out std_logic_vector (47 downto 0);
+    casc_o : out std_logic_vector (47 downto 0)
+  );
+  end component;
+
+  signal data_se  : std_logic_vector(17 downto 0);
+  signal data_int : std_logic_vector(data_o'range);  
+
+begin
+
+  coef <= (
+     0 => conv_std_logic_vector(   186968, 25),
+     1 => conv_std_logic_vector(   363532, 25),
+     2 => conv_std_logic_vector(   192469, 25),
+     3 => conv_std_logic_vector(  -714736, 25),
+     4 => conv_std_logic_vector( -2294800, 25),
+     5 => conv_std_logic_vector( -3865066, 25),
+     6 => conv_std_logic_vector( 12250263, 25),
+     7 => conv_std_logic_vector( -3865066, 25),
+     8 => conv_std_logic_vector( -2294800, 25),
+     9 => conv_std_logic_vector(  -714736, 25),
+    10 => conv_std_logic_vector(   192469, 25),
+    11 => conv_std_logic_vector(   363532, 25),
+    12 => conv_std_logic_vector(   186968, 25)
+  );
+
+  cmp_mac_first : mac1reg
+  port map
+  (
+    clk_i  => clk_i,
+    data_i => data_se,
+    coef_i => coef(0),
+    data_o => data(0),
+    casc_o => cascade(0)
+  );
+
+  gen_mac_cascade : for i in 1 to 11 generate
+    cmp_mac : mac2reg
+    port map
+    (
+      clk_i  => clk_i,
+      data_i => data(i-1),
+      coef_i => coef(i),
+      casc_i => cascade(i-1),
+      data_o => data(i),
+      mac_o => open,
+      casc_o => cascade(i) 
+    );
+  end generate;
+
+  cmp_mac_last : mac2reg
+   port map
+   (
+     clk_i  => clk_i,
+     data_i => data(11),
+     coef_i => coef(12),
+     casc_i => cascade(11),
+     data_o => open,
+     mac_o => data_full,
+     casc_o => open
+   );
+
+   data_se(15 downto 0) <= data_i;
+   data_se(17 downto 16) <= (others => data_i(15));
+
+   -- Truncate 7 MSB and 25 LSB to achieve better precision at the output
+   -- TODO: verify if this is the optimal solution
+   data_o <= data_full(40 downto 25);
+
+end rtl;

hdl/modules/hpf_adcinput/mac1reg.vhd

@@ -0,0 +1,139 @@
+------------------------------------------------------------------------------
+-- Title      : DSP48E1-based MAC and data registered data propagation (1 stage)
+------------------------------------------------------------------------------
+-- Author     : Daniel Tavares
+-- Company    : CNPEM LNLS-DIG
+-- Created    : 2019-11-23
+-- Platform   : FPGA-generic
+-------------------------------------------------------------------------------
+-- Description: Elementary mulitply-accumulate block for systolic FIR filter
+--              implementation. Use 1 pipeline stage at the input data.
+--              Reference: "DSP: Designing for Optimal Results"
+-------------------------------------------------------------------------------
+-- Copyright (c) 2019 CNPEM
+-- Licensed under GNU Lesser General Public License (LGPL) v3.0
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author              Description
+-- 2019-11-23  1.0      daniel.tavares      Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_signed.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity mac1reg is
+port
+(
+  clk_i  : in  std_logic;
+  data_i : in  std_logic_vector (17 downto 0);
+  coef_i : in  std_logic_vector (24 downto 0);
+  data_o : out std_logic_vector (17 downto 0);
+  mac_o :  out std_logic_vector (47 downto 0);
+  casc_o : out std_logic_vector (47 downto 0)
+);
+end mac1reg;
+
+architecture rtl of mac1reg is
+
+  signal coef : std_logic_vector(29 downto 0);
+
+begin
+
+  DSP48E1_inst : DSP48E1
+  generic map (
+    -- Feature Control Attributes: Data Path Selection
+    A_INPUT => "DIRECT",
+    B_INPUT => "DIRECT",
+    USE_DPORT => FALSE,
+    USE_MULT => "MULTIPLY",
+    USE_SIMD => "ONE48",
+    -- Pattern Detector Attributes: Pattern Detection Configuration
+    AUTORESET_PATDET => "NO_RESET", 
+    MASK => X"3fffffffffff",
+    PATTERN => X"000000000000",
+    SEL_MASK => "MASK", 
+    SEL_PATTERN => "PATTERN",
+    USE_PATTERN_DETECT => "NO_PATDET",
+    -- Register Control Attributes: Pipeline Register Configuration
+    ACASCREG => 1,
+    ADREG => 1,
+    ALUMODEREG => 1,
+    AREG => 1,
+    BCASCREG => 1,
+    BREG => 1,
+    CARRYINREG => 0,
+    CARRYINSELREG => 0,
+    CREG => 1,
+    DREG => 1,
+    INMODEREG => 0,
+    MREG => 1,
+    OPMODEREG => 0,
+    PREG => 1
+  )
+  port map (
+    CLK => clk_i,            
+
+    A => coef,
+    B => data_i,
+    BCOUT => data_o,
+    PCOUT => casc_o,
+    P => mac_o,
+    BCIN => (others => '0'),
+    PCIN => (others => '0'),
+    INMODE => "10001",
+    OPMODE => "0000101",
+    ALUMODE => "0000",
+
+    -- Reset/Clock Enable Inputs
+    CEA1 => '1',
+    CEA2 => '0',
+    CEAD => '0',
+    CEALUMODE => '1',
+    CEB1 => '1',
+    CEB2 => '1',
+    CEC => '0',
+    CECARRYIN => '0',
+    CECTRL => '1',
+    CED => '0',
+    CEINMODE => '0',
+    CEM => '1',
+    CEP => '1',
+    RSTA => '0',           
+    RSTALLCARRYIN => '0',  
+    RSTALUMODE => '0',     
+    RSTB => '0',           
+    RSTC => '0',           
+    RSTCTRL => '0',        
+    RSTD => '0',           
+    RSTINMODE => '0',      
+    RSTM => '0',           
+    RSTP => '0',
+
+    -- Unused port
+    ACOUT => open,
+    CARRYCASCOUT => open,
+    MULTSIGNOUT => open,
+    OVERFLOW => open,
+    PATTERNBDETECT => open,
+    PATTERNDETECT => open,
+    UNDERFLOW => open,
+    CARRYOUT => open,
+    ACIN => (others => '0'),
+    CARRYCASCIN => '0',
+    MULTSIGNIN => '0',
+    CARRYINSEL => "000",
+    C => (others => '0'),
+    CARRYIN => '0',
+    D => (others => '0')
+  );
+
+  -- Sign extension - DSP48E1 expects 30 bits on port A but multiplier uses only 25 bits
+  coef(24 downto 0) <= coef_i;
+  coef(29 downto 25) <= (others => coef_i(24));
+
+end rtl;