[ci] Add Yosys synthesis flow #1501
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added 7 commits
January 3, 2022 09:22
Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>
Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>
Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>
Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>
Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>
Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>
Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>
rswarbrick
reviewed
Jan 12, 2022
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Wow, it's cool that this works!
One question: The first commit adds a special core file for the UHDM flow. Eventually, I assume we'd want to combine this with the existing core files (since we're just specifying a different tool). Is there a reason that's difficult at the moment?
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I based this on a patch we use to add other targets, but I don't think there will be any problem with rolling that into the existing core. I agree that it would be cleaner. |
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Opening a draft PR to get some early input and suggestions.
As proposed in #1481, this PR adds a Github action workflow that synthesizes Ibex via Yosys, using Surelog-UHDM frontend.
It obtains a release from Antmicro's plugin repository and edalize fork (until UHDM support is merged in lowRISC/edalize#3).
Each flow generates an EDIF artifact that can be downloaded and processed further locally.