Fixing non-simplified gates handling in networks #632
Merged
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This PR solves a bug that may occur when using the methods
substitute_node_no_restrash
orreplace_in_node_no_restrash
.In particular, these methods may create non-simplified gates such as buffer nodes. For instance, in an AIG, a buffer could be seen as an AND node where both fanins are connected to the same node with the same phase. In this case, this node is seen as a PI or a CI according to the previous code. This PR solves this issue by reserving the unused field
data[1].h2
to track if a node is a PI or CI.Moreover, another related issue is present in the XAG and XMG networks. In
xag_network
, AND and XOR are distinguished by the ordering of the indexes such that AND:index0 < index1
, and XOR:index0 > index1
. The behavior is undefined whenindex0 = index1
.The proposed patch treats the equal case as an AND. When
index0 = index1
is an XOR gate, the gate is transformed into an AND gate by setting the inputs to constants, i.e. by performing the simplification. XMGs handles this case similarly by treating the equal case as an MAJ3 gate.Finally, this PR includes runtime improvements to
air_balance
andxag_balance
, which had long run times on very large benchmarks. The default optimization method to improve size has been reduced from quadratic to linear complexity, in terms of the number of nodes. The old version is available by setting the parameterfast_mode
to false.