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Designing simple 5-stage pipelined RISC-V processor (Lab assignment of "Computer Architecture" class)

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Name		Name	Last commit message	Last commit date
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Lab1		Lab1
Lab2		Lab2
Lab3		Lab3
Lab4		Lab4
.gitignore		.gitignore
README.md		README.md

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Processor Design

Designing and simlating simple 5-stage pipelined RISC-V processor using SystemVelilog and ModelSim

Lab assignment of 2020-2R "Computer Architecture" class

Lab 1: Instruction Design (Score 5/5)

Lab 2: Datapath Element Design (Score 20/20)

Lab 3: Single-cycle Processor Design (Score 30/30)

Lab 4: 5-stage Pipelined Processor Design (Score 45/45)

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Designing simple 5-stage pipelined RISC-V processor (Lab assignment of "Computer Architecture" class)

systemverilog computer-architecture pipeline-processor processor-design

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