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.gitignore
.gitignore
 
 
ALU.bsf
ALU.bsf
 
 
ALU.v
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BUS.bsf
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BUS.v
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CON_FF.v
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DesignProject.bdf
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DesignProject.qpf
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DesignProject.qsf
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DesignProject_tb.bsf
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DesignProject_tb.v
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IncPCModule.bsf
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IncPCModule.v
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LICENSE
LICENSE
 
 
MAR.v
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MDR.bsf
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MDR.v
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README.md
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Register.bsf
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Register_0.v
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add_32_gate.bsf
add_32_gate.bsf
 
 
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addi_tb.v
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and_32_gate.bsf
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andi_tb.v
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brmi_tb.v
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brnz_tb.v
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brpl_tb.v
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brzr_tb.v
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control_unit.v
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datapath.bsf
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datapath.v
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div_32_gate.v
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inPort.v
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inPort_tb.v
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jal_tb.v
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jr_tb.v
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ld_tb.v
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ldi_tb.v
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memory.hex
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mfhi_tb.v
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mflo_tb.v
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mul_32_gate.v
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neg_32_gate.v
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not_32_gate.bsf
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or_32_gate.bsf
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or_32_gate.v
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ori_tb.v
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outPort.v
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ram.v
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ram2.bsf
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ram2_bb.v
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ram2_inst.v
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reg_32_bits.bsf
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register.v
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rol_32_gate.v
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ror_32_gate.v
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select_encode_logic.v
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shl_32_gate.bsf
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shr_32_gate.bsf
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st_tb.v
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sub_32_gate.bsf
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sub_32_gate.v
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ELEC 374

Final project for ELEC 374 Digital Systems Engineering W22 to design a Simple RISC Computer using Verilog.

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ELEC374 is available under the MIT license. See the LICENSE file for more info.

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A simple RISC computer built using Verilog

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