This repository contains the source code for my Minimal RISC-V SoC.
To view the datasheet and full documentation set associated with this project, click here.
Note
This project is a work in progress. I'm picking this up in my free time as and when I can.
To run simulations, view waveforms, and flash Lattice/Gowin FPGAs, you'll need the latest version of the OSS CAD suite. For Xilinx FPGAs, Vivado is required.
All Makefiles rely on the $ROOT variable being set, which you can get by
sourcing the appropriately named sourceme file.
Full information on running simulations and the project setup are available on the project page.
Matias Wang Silva, 2024/2025
MIT