Skip to content

mattvenn/wokwi-verilog-gds-test

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

68 Commits
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Go to https://tinytapeout.com for instructions!

Out of date!

We have a new submission repo now: https://github.com/TinyTapeout/tt02-submission-template

How to change the Wokwi project

Edit the Makefile and change the WOKWI_PROJECT_ID to match your project.

What is this about?

This repo is a template you can make a copy of for your own ASIC design using Wokwi.

When you edit the Makefile to choose a different ID, the GitHub Action will fetch the digital netlist of your design from Wokwi.

The design gets wrapped in some extra logic that builds a 'scan chain'. This is a way to put lots of designs onto one chip and still have access to them all. You can see all of the technical details here.

After that, the action uses the open source ASIC tool called OpenLane to build the files needed to fabricate an ASIC.

What files get made?

When the action is complete, you can click here to see the latest build of your design. You need to download the zip file and take a look at the contents:

  • gds_render.svg - picture of your ASIC design
  • gds.html - zoomable picture of your ASIC design
  • runs/wokwi/reports/final_summary_report.csv - CSV file with lots of details about the design
  • runs/wokwi/reports/synthesis/1-synthesis.stat.rpt.strategy4 - list of the standard cells used by your design
  • runs/wokwi/results/final/gds/user_module.gds - the final GDS file needed to make your design

What next?