Fix to interleaving interrupts with floating-point operations #7
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The size of the array holding the floating point registers was extended by a factor of 8, as many as available PL-PS interrupts on an Ultrascale+ platform.
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Following discussion offline, the maximum reasonable number of interleaved interrupts on Ultrascale+ is 8, so that's the best choice for size extension of the context buffer storing floating-point registers during pre-empting of interrupts using floating-point values. Let me know, @mcejp, if you have any other comments or suggestions regarding this PR. |
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This PR resolves the observed issue with interleaving interrupts using floating-point registers and with different priority levels, as reported in #5.
The size of the array holding the floating point registers was extended by a factor of 16, as many as available PL-PS interrupts on an Ultrascale+ platform, following information from table 13-1 from the Ultrascale+ technical manual.
I intended to add a payload allowing future users to run a test on their hardware to make sure it is resolved. However, I didn't find a way to do so without making assumptions about the FPGA IP cores existing on the given device. Therefore, unless @mcejp has an idea how to achieve that, I propose to merge it as-is. I have tested it on an Ultrascale+ of the CERN's FGC4 project, where we have over 8 available interrupt sources in the FPGA, and they all were successfully interleaving in my manual tests. I will add this to the FGC4 code repository.