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1. FazyRV FazyRV Public

   A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

   SystemVerilog 74 4

2. FazyRV-ExoTiny FazyRV-ExoTiny Public

   Assembly 1 1

3. tt06-FazyRV-ExoTiny tt06-FazyRV-ExoTiny Public

   SystemVerilog 1

4. RV32I_SC_Logisim RV32I_SC_Logisim Public

   A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

   Verilog 3

5. logIP logIP Public

   Logic Analyzer IP Core

   SystemVerilog 5

6. SimIO SimIO Public

   SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.

   Python 8