Multicycle RISC-V CPU

This is an implementation of multicycle RISC-V CPU. It supports RV32I_Zicsr and interrupts. Tested with RISCOF.

Dependencies

• Verilator
• RISCOF
• Spike
• riscv-gnu-toolchain
  • Use --with-arch=rv32i_zicsr when building

Running Tests

Note: Make sure the Spike and toolchain binaries are visible via $PATH

$ git clone https://github.com/mmichilot/RISCV-multicycle
$ cd RISCV-multicycle
$ make