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Replace numStages with more elaborate processor structure info #203
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numStages is only sensible for single issue processors. In this commit, we introduce the ProcessorStructure type, a 2d mapping suitable for communicating more information about the datapath of a processor.
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@mortbopet
mortbopet committed Mar 26, 2022
1 parent 99bf9ab commit 2048c66
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Showing 19 changed files with 416 additions and 332 deletions.
46 changes: 25 additions & 21 deletions src/editor/codeeditor.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -442,30 +442,34 @@ void CodeEditor::updateHighlighting() {

// Iterate over the processor stages and use the source mappings to determine
// the source line which originated the instruction.
const unsigned stages = proc->stageCount();
const unsigned stages = proc->structure().numStages();
auto colorGenerator = Colors::incrementalRedGenerator(stages);

for (unsigned sid = 0; sid < stages; sid++) {
const auto stageInfo = proc->stageInfo(sid);
QColor stageColor = colorGenerator();
if (stageInfo.stage_valid) {
auto mappingIt = sourceMapping.find(stageInfo.pc);
if (mappingIt == sourceMapping.end()) {
// No source line registerred for this PC.
continue;
}

for (auto sourceLine : mappingIt->second) {
// Find block
QTextBlock block = document()->findBlockByLineNumber(sourceLine);
if (!block.isValid())
for (auto laneIt : proc->structure()) {
for (unsigned stageIdx = 0; stageIdx < laneIt.second; stageIdx++) {
StageIndex sid = StageIndex{laneIt.first, stageIdx};
const auto stageInfo = proc->stageInfo(sid);
QColor stageColor = colorGenerator();
if (stageInfo.stage_valid) {
auto mappingIt = sourceMapping.find(stageInfo.pc);
if (mappingIt == sourceMapping.end()) {
// No source line registerred for this PC.
continue;

// Record the stage name for the highlighted block for later painting
QString stageString = ProcessorHandler::getProcessor()->stageName(sid);
if (!stageInfo.namedState.isEmpty())
stageString += " (" + stageInfo.namedState + ")";
highlightBlock(block, stageColor, stageString);
}

for (auto sourceLine : mappingIt->second) {
// Find block
QTextBlock block = document()->findBlockByLineNumber(sourceLine);
if (!block.isValid())
continue;

// Record the stage name for the highlighted block for later painting
QString stageString =
ProcessorHandler::getProcessor()->stageName(sid);
if (!stageInfo.namedState.isEmpty())
stageString += " (" + stageInfo.namedState + ")";
highlightBlock(block, stageColor, stageString);
}
}
}
}
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60 changes: 32 additions & 28 deletions src/instructionmodel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -27,10 +27,12 @@ int InstructionModel::addressToRow(AInt addr) const {

InstructionModel::InstructionModel(QObject *parent)
: QAbstractTableModel(parent) {
for (unsigned i = 0; i < ProcessorHandler::getProcessor()->stageCount();
++i) {
m_stageNames << ProcessorHandler::getProcessor()->stageName(i);
m_stageInfos[i];
for (auto laneIt : ProcessorHandler::getProcessor()->structure()) {
for (unsigned stageIdx = 0; stageIdx < laneIt.second; stageIdx++) {
StageIndex idx = {laneIt.first, stageIdx};
m_stageNames[idx] = ProcessorHandler::getProcessor()->stageName(idx);
m_stageInfos[idx] = ProcessorHandler::getProcessor()->stageInfo(idx);
}
}
connect(ProcessorHandler::get(), &ProcessorHandler::procStateChangedNonRun,
this, &InstructionModel::updateStageInfo);
Expand Down Expand Up @@ -65,31 +67,33 @@ int InstructionModel::rowCount(const QModelIndex &) const { return m_rowCount; }

void InstructionModel::updateStageInfo() {
bool firstStageChanged = false;
for (unsigned i = 0; i < ProcessorHandler::getProcessor()->stageCount();
++i) {
if (static_cast<unsigned>(m_stageInfos.size()) > i) {
auto &oldStageInfo = m_stageInfos.at(i);
if (i == 0) {
if (oldStageInfo.pc !=
ProcessorHandler::getProcessor()->stageInfo(i).pc) {
firstStageChanged = true;
for (auto laneIt : ProcessorHandler::getProcessor()->structure()) {
for (unsigned stageIdx = 0; stageIdx < laneIt.second; stageIdx++) {
StageIndex idx = {laneIt.first, stageIdx};
auto stageInfoIt = m_stageInfos.find(idx);
if (stageInfoIt != m_stageInfos.end()) {
auto &oldStageInfo = m_stageInfos.at(idx);
if (idx == StageIndex(0, 0)) {
if (oldStageInfo.pc !=
ProcessorHandler::getProcessor()->stageInfo(idx).pc) {
firstStageChanged = true;
}
}
const auto stageInfo = ProcessorHandler::getProcessor()->stageInfo(idx);
const AInt oldAddress = oldStageInfo.pc;
if (oldStageInfo != stageInfo) {
oldStageInfo = stageInfo;
const int oldRow = addressToRow(oldAddress);
const int newRow = addressToRow(stageInfo.pc);
const QModelIndex oldIdx = index(oldRow, Stage);
const QModelIndex newIdx = index(newRow, Stage);
emit dataChanged(oldIdx, oldIdx, {Qt::DisplayRole});
emit dataChanged(newIdx, newIdx, {Qt::DisplayRole});
}
if (firstStageChanged) {
emit firstStageInstrChanged(addressToRow(m_stageInfos.at({0, 0}).pc));
firstStageChanged = false;
}
}
const auto stageInfo = ProcessorHandler::getProcessor()->stageInfo(i);
const AInt oldAddress = oldStageInfo.pc;
const bool stageInfoChanged = oldStageInfo != stageInfo;
oldStageInfo = stageInfo;
if (stageInfoChanged) {
const int oldRow = addressToRow(oldAddress);
const int newRow = addressToRow(stageInfo.pc);
const QModelIndex oldIdx = index(oldRow, Stage);
const QModelIndex newIdx = index(newRow, Stage);
emit dataChanged(oldIdx, oldIdx, {Qt::DisplayRole});
emit dataChanged(newIdx, newIdx, {Qt::DisplayRole});
}
if (firstStageChanged) {
emit firstStageInstrChanged(addressToRow(m_stageInfos.at(0).pc));
firstStageChanged = false;
}
}
}
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4 changes: 2 additions & 2 deletions src/instructionmodel.h
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Original file line number Diff line number Diff line change
Expand Up @@ -52,9 +52,9 @@ class InstructionModel : public QAbstractTableModel {
void onProcessorReset();

std::shared_ptr<const Program> m_program;
QStringList m_stageNames;
std::map<StageIndex, QString> m_stageNames;
using StageID = unsigned;
std::map<StageID, StageInfo> m_stageInfos;
std::map<StageIndex, StageInfo> m_stageInfos;
int m_rowCount = 0;
};
} // namespace Ripes
10 changes: 6 additions & 4 deletions src/pipelinediagrammodel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -76,10 +76,12 @@ void PipelineDiagramModel::gatherStageInfo() {
if (stageInfoForCycle == m_cycleStageInfos.end()) {
return;
}
for (unsigned i = 0; i < ProcessorHandler::getProcessor()->stageCount();
++i) {
stageInfoForCycle->second[i] =
ProcessorHandler::getProcessor()->stageInfo(i);
for (auto laneIt : ProcessorHandler::getProcessor()->structure()) {
for (unsigned stageIdx = 0; stageIdx < laneIt.second; stageIdx++) {
StageIndex idx = {laneIt.first, stageIdx};
stageInfoForCycle->second[idx] =
ProcessorHandler::getProcessor()->stageInfo(idx);
}
}
}

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2 changes: 1 addition & 1 deletion src/pipelinediagrammodel.h
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ public slots:
* @brief m_cycleStageInfos
* map<cycle, map<stageId, stageInfo>>
*/
std::map<long long, std::map<unsigned, StageInfo>> m_cycleStageInfos;
std::map<long long, std::map<StageIndex, StageInfo>> m_cycleStageInfos;

/**
* @brief m_atMaxCycles
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76 changes: 54 additions & 22 deletions src/processorregistry.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -19,10 +19,10 @@ ProcessorRegistry::ProcessorRegistry() {
// RISC-V single cycle
layouts = {{"Standard",
":/layouts/RISC-V/rvss/rv_ss_standard_layout.json",
{QPointF{0.5, 0}}},
{{{0, 0}, QPointF{0.5, 0}}}},
{"Extended",
":/layouts/RISC-V/rvss/rv_ss_extended_layout.json",
{QPointF{0.5, 0}}}};
{{{0, 0}, QPointF{0.5, 0}}}}};
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
addProcessor(ProcInfo<vsrtl::core::RVSS<uint32_t>>(
ProcessorID::RV32_SS, "Single-cycle processor",
Expand All @@ -35,12 +35,18 @@ ProcessorRegistry::ProcessorRegistry() {
layouts = {
{"Standard",
":/layouts/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.54, 0}, QPointF{0.73, 0},
QPointF{0.88, 0}}},
{{{0, 0}, QPointF{0.08, 0}},
{{0, 1}, QPointF{0.3, 0}},
{{0, 2}, QPointF{0.54, 0}},
{{0, 3}, QPointF{0.73, 0}},
{{0, 4}, QPointF{0.88, 0}}}},
{"Extended",
":/layouts/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json",
{QPointF{0.08, 0.0}, QPointF{0.31, 0.0}, QPointF{0.56, 0.0},
QPointF{0.76, 0.0}, QPointF{0.9, 0.0}}}};
{{{0, 0}, QPointF{0.08, 0.0}},
{{0, 1}, QPointF{0.31, 0.0}},
{{0, 2}, QPointF{0.56, 0.0}},
{{0, 3}, QPointF{0.76, 0.0}},
{{0, 4}, QPointF{0.9, 0.0}}}}};
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
addProcessor(ProcInfo<vsrtl::core::RV5S_NO_FW_HZ<uint32_t>>(
ProcessorID::RV32_5S_NO_FW_HZ,
Expand All @@ -58,12 +64,18 @@ ProcessorRegistry::ProcessorRegistry() {
// RISC-V 5-stage without hazard detection
layouts = {{"Standard",
":/layouts/RISC-V/rv5s_no_hz/rv5s_no_hz_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.53, 0},
QPointF{0.75, 0}, QPointF{0.88, 0}}},
{{{0, 0}, QPointF{0.08, 0}},
{{0, 1}, QPointF{0.3, 0}},
{{0, 2}, QPointF{0.53, 0}},
{{0, 3}, QPointF{0.75, 0}},
{{0, 4}, QPointF{0.88, 0}}}},
{"Extended",
":/layouts/RISC-V/rv5s_no_hz/rv5s_no_hz_extended_layout.json",
{QPointF{0.08, 0}, QPointF{0.28, 0}, QPointF{0.53, 0},
QPointF{0.78, 0}, QPointF{0.9, 0}}}};
{{{0, 0}, QPointF{0.08, 0}},
{{0, 1}, QPointF{0.28, 0}},
{{0, 2}, QPointF{0.53, 0}},
{{0, 3}, QPointF{0.78, 0}},
{{0, 4}, QPointF{0.9, 0}}}}};
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
addProcessor(ProcInfo<vsrtl::core::RV5S_NO_HZ<uint32_t>>(
ProcessorID::RV32_5S_NO_HZ, "5-stage processor w/o hazard detection",
Expand All @@ -79,12 +91,18 @@ ProcessorRegistry::ProcessorRegistry() {
// RISC-V 5-stage without forwarding unit
layouts = {{"Standard",
":/layouts/RISC-V/rv5s_no_fw/rv5s_no_fw_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.53, 0},
QPointF{0.75, 0}, QPointF{0.88, 0}}},
{{{0, 0}, QPointF{0.08, 0}},
{{0, 1}, QPointF{0.3, 0}},
{{0, 2}, QPointF{0.53, 0}},
{{0, 3}, QPointF{0.75, 0}},
{{0, 4}, QPointF{0.88, 0}}}},
{"Extended",
":/layouts/RISC-V/rv5s_no_fw/rv5s_no_fw_extended_layout.json",
{QPointF{0.08, 0}, QPointF{0.28, 0}, QPointF{0.53, 0},
QPointF{0.78, 0}, QPointF{0.9, 0}}}};
{{{0, 0}, QPointF{0.08, 0}},
{{0, 1}, QPointF{0.28, 0}},
{{0, 2}, QPointF{0.53, 0}},
{{0, 3}, QPointF{0.78, 0}},
{{0, 4}, QPointF{0.9, 0}}}}};
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
addProcessor(ProcInfo<vsrtl::core::RV5S_NO_FW<uint32_t>>(
ProcessorID::RV32_5S_NO_FW, "5-Stage processor w/o forwarding unit",
Expand All @@ -100,12 +118,18 @@ ProcessorRegistry::ProcessorRegistry() {
// RISC-V 5-stage
layouts = {{"Standard",
":/layouts/RISC-V/rv5s/rv5s_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.29, 0}, QPointF{0.55, 0},
QPointF{0.75, 0}, QPointF{0.87, 0}}},
{{{0, 0}, QPointF{0.08, 0}},
{{0, 1}, QPointF{0.29, 0}},
{{0, 2}, QPointF{0.55, 0}},
{{0, 3}, QPointF{0.75, 0}},
{{0, 4}, QPointF{0.87, 0}}}},
{"Extended",
":/layouts/RISC-V/rv5s/rv5s_extended_layout.json",
{QPointF{0.08, 0}, QPointF{0.28, 0}, QPointF{0.54, 0},
QPointF{0.78, 0}, QPointF{0.9, 0}}}};
{{{0, 1}, QPointF{0.08, 0}},
{{0, 2}, QPointF{0.28, 0}},
{{0, 3}, QPointF{0.54, 0}},
{{0, 4}, QPointF{0.78, 0}},
{{0, 5}, QPointF{0.9, 0}}}}};
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
addProcessor(ProcInfo<vsrtl::core::RV5S<uint32_t>>(
ProcessorID::RV32_5S, "5-stage processor",
Expand All @@ -121,10 +145,18 @@ ProcessorRegistry::ProcessorRegistry() {
// RISC-V 6-stage dual issue
layouts = {{"Extended",
":/layouts/RISC-V/rv6s_dual/rv6s_dual_extended_layout.json",
{{QPointF{0.06, 0}, QPointF{0.06, 1}, QPointF{0.22, 0},
QPointF{0.22, 1}, QPointF{0.40, 0}, QPointF{0.40, 1},
QPointF{0.59, 0}, QPointF{0.59, 1}, QPointF{0.80, 0},
QPointF{0.80, 1}, QPointF{0.90, 0}, QPointF{0.90, 1}}}}};
{{{{0, 0}, QPointF{0.06, 0}},
{{1, 0}, QPointF{0.06, 1}},
{{0, 1}, QPointF{0.22, 0}},
{{1, 1}, QPointF{0.22, 1}},
{{0, 2}, QPointF{0.40, 0}},
{{1, 2}, QPointF{0.40, 1}},
{{0, 3}, QPointF{0.59, 0}},
{{1, 3}, QPointF{0.59, 1}},
{{0, 4}, QPointF{0.80, 0}},
{{1, 4}, QPointF{0.80, 1}},
{{0, 5}, QPointF{0.90, 0}},
{{1, 5}, QPointF{0.90, 1}}}}}};
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
addProcessor(ProcInfo<vsrtl::core::RV6S_DUAL<uint32_t>>(
ProcessorID::RV32_6S_DUAL, "6-stage dual-issue processor",
Expand Down
2 changes: 1 addition & 1 deletion src/processorregistry.h
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Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ struct Layout {
* labels can be "stacked" over one another. Must contain an entry for each
* stage in the processor model.
*/
std::vector<QPointF> stageLabelPositions;
std::map<StageIndex, QPointF> stageLabelPositions;
bool operator==(const Layout &rhs) const { return this->name == rhs.name; }
};

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