Added translation using Weblate (Spanish)

source/locale/es/LC_MESSAGES/SpinalHDL/Libraries/bus_slave_factory.po

@@ -0,0 +1,246 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: Automatically generated\n"
+"Language-Team: none\n"
+"Language: es\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:7
+msgid "Bus Slave Factory"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:10
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:12
+msgid "In many situation it's needed to implement a bus register bank. The ``BusSlaveFactory`` is a tool that provide an abstract and smooth way to define them."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:14
+msgid "To see capabilities of the tool, an simple example use the Apb3SlaveFactory variation to implement an :ref:`memory mapped UART <memory_mapped_uart>`. There is also another example with an :ref:`Timer <timer>` which contain a memory mapping function."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:16
+msgid "You can find more documentation about the internal implementation of the ``BusSlaveFactory`` tool :ref:`there <bus_slave_factory_implementation>`"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:19
+msgid "Functionality"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:21
+msgid "There are many implementations of the ``BusSlaveFactory`` tool : AHB3-lite, APB3, APB4, AvalonMM, AXI-lite 3, AXI4, BMB, Wishbone and PipelinedMemoryBus."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:22
+msgid "Each implementation of that tool take as an argument one instance of the corresponding bus and then offers the following functions to map your hardware into the memory mapping :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:28
+msgid "Name"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:29
+msgid "Return"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:30
+msgid "Description"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:31
+msgid "busDataWidth"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:32
+msgid "Int"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:33
+msgid "Return the data width of the bus"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:34
+msgid "read(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:36
+msgid "When the bus read the ``address``\\ , fill the response with ``that`` at ``bitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:37
+msgid "write(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:39
+msgid "When the bus write the ``address``\\ , assign ``that`` with bus's data from ``bitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:40
+msgid "onWrite(address)(doThat)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:42
+msgid "Call ``doThat`` when a write transaction occur on ``address``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:43
+msgid "onRead(address)(doThat)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:45
+msgid "Call ``doThat`` when a read transaction occur on ``address``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:46
+msgid "nonStopWrite(that,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:48
+msgid "Permanently assign ``that`` by the bus write data from ``bitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:49
+msgid "readAndWrite(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:51
+msgid "Make ``that`` readable and writable at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:52
+msgid "readMultiWord(that,address)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "Create the memory mapping to read ``that`` from 'address'."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "If ``that`` is bigger than one word it extends the register on followings addresses"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:56
+msgid "writeMultiWord(that,address)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "Create the memory mapping to write ``that`` at 'address'."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:60
+msgid "createWriteOnly(dataType,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:61
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:64
+msgid "T"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:62
+msgid "Create a write only register of type ``dataType`` at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:63
+msgid "createReadWrite(dataType,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:65
+msgid "Create a read write register of type ``dataType`` at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:66
+msgid "createAndDriveFlow(dataType,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:67
+msgid "Flow[T]"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:68
+msgid "Create a writable Flow register of type ``dataType`` at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:69
+msgid "drive(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:71
+msgid "Drive ``that`` with a register writable at ``address`` placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:72
+msgid "driveAndRead(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:74
+msgid "Drive ``that`` with a register writable and readable at ``address`` placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:75
+msgid "driveFlow(that,address,bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:77
+msgid "Emit on ``that`` a transaction when a write happen at ``address`` by using data placed at ``bitOffset`` in the word"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "readStreamNonBlocking(that,"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "address,"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "validBitOffset,"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "payloadBitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "Read ``that`` and consume the transaction when a read happen at ``address``."
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "valid <= validBitOffset bit"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "payload <= payloadBitOffset+widthOf(payload) downto ``payloadBitOffset``"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "doBitsAccumulationAndClearOnRead(that,"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "bitOffset)"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "Instantiate an internal register which at each cycle do :"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "reg := reg | that"
+msgstr ""
+
+#: ../../SpinalHDL/Libraries/bus_slave_factory.rst:0
+msgid "Then when a read occur, the register is cleared. This register is readable at ``address`` and placed at ``bitOffset`` in the word"
+msgstr ""