Added translation using Weblate (Spanish)

source/locale/es/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po

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+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2018 - 2024, SpinalHDL
+# This file is distributed under the same license as the SpinalHDL package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: SpinalHDL\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2024-01-02 16:09+0000\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: Automatically generated\n"
+"Language-Team: none\n"
+"Language: es\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:4
+msgid "Slots"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:7
+msgid "Introduction"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:9
+msgid "Let's say you have some hardware which has to keep track of multiple similar ongoing activities, you may want to implement an array of \"slots\" to do so. This example show how to do it using Area, OHMasking.first, onMask and reader."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:13
+msgid "Implementation"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:15
+msgid "This implementation avoid the use of Vec. Instead, it use Area which allow to mix signal, registers and logic definitions in each slot."
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:17
+msgid "Note that the `reader` API is for SpinalHDL version comming after 1.9.1"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:24
+msgid "In practice"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:26
+msgid "For instance, this kind of slot pattern is used in Tilelink coherency hub to keep track of all ongoing memory probes in flight:"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:28
+msgid "https://github.com/SpinalHDL/SpinalHDL/blob/008c73f1ce18e294f137efe7a1442bd3f8fa2ee0/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Hub.scala#L376"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:30
+msgid "As well in the DRAM / SDR / DDR memory controller to implement the handeling of multiple memory transactions at once (having multiple precharge / active / read / write running at the same time to improve performances) :"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:32
+msgid "https://github.com/SpinalHDL/SpinalHDL/blob/1edba1890b5f629b28e5171b3c449155337d2548/lib/src/main/scala/spinal/lib/memory/sdram/xdr/Tasker.scala#L202"
+msgstr ""
+
+#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:34
+msgid "As well in the NaxRiscv (out of order CPU) load-store-unit to handle the store-queue / load-queue hardware (a bit too scary to show here in the doc XD)"
+msgstr ""