APU enhancement

CHANGELOG.md

@@ -1,5 +1,8 @@
 # Changes
 
+[25.06.2024]
+- Add APU enhancement on top of cheat engine
+
 [20.03.2024]
 - Add CHANGELOG.md
 - Set device in nestang_nano20k.gprj

doc/cheats.md

@@ -0,0 +1,35 @@
+# Cheat Wizard
+
+## Format
+
+This new module accepts `*.cwz` binary files with the following format:
+
+- 128 bits (16 bytes) per cheat
+    - Four bytes correspond to compare enabled/disabled
+    - Next 4 bytes correspond to address
+    - Next 4 bytes correspond to compare value
+    - Next 4 bytes correspond to replace value
+
+Example for `Battletoads.nes`
+
+```
+00000001 00000320 00000000 00000004
+00000001 000023a2 000000d6 00000024
+00000001 000026b5 00000001 00000000
+00000001 00004fba 00000008 0000002f
+...
+```
+
+You'll need to use a hex editor to create the file.
+
+## How to use
+
+# Enable cheats
+
+Navigate to `2)Options->Cheats->Cheats Enabled:` and press `A` to enable or disable.
+
+## Load a cheat file
+
+Navigate to `2)Options->Cheats->Load cheat file` and press `A` to open the file explorer view. Choose the `.cwz` file for your game and press `A`, you'll see the message `Cheats loaded!` if the file was correctly loaded.
+
+After enabling cheats and loading them, you can load a `ROM` and cheats will be applied.

doc/wishbone.md

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+# Pipelined Wishbone B4 Bus
+
+## About
+
+- `iosys` is wishbone master
+- No `FIFO` implemented
+- No arbiter implemented
+- 128bit wide bus for `cheat_wizard`
+
+- Slaves
+    - `wishbone_slaves.sh`
+
+## Read
+
+<img src="images/wishbone_b4_piplined_singleReadCycle.JPG" width=400>
+
+## Write
+
+<img src="images/wishbone_b4_piplined_singleWriteCycle.JPG" width=400>
+
+## References
+
+- [Wishbone bus](https://en.wikipedia.org/wiki/Wishbone_(computer_bus))
+- [Wishbone B4 Specifications](https://cdn.opencores.org/downloads/wbspec_b4.pdf)
+- [zipcpu](https://zipcpu.com/)
+- [Building a simple bus](https://zipcpu.com/zipcpu/2017/05/23/simplebus.html)
+- [Building a Simple Wishbone Master](https://zipcpu.com/blog/2017/06/08/simple-wb-master.html)
+- [Building a Simple Wishbone Slave](https://zipcpu.com/zipcpu/2017/05/29/simple-wishbone.html)
+- [Building Formal Assumptions to Describe Wishbone Behaviour](https://zipcpu.com/zipcpu/2017/11/07/wb-formal.html)
+- [Building a very simple wishbone interconnect](https://zipcpu.com/blog/2017/06/22/simple-wb-interconnect.html)

nestang-0.11.1_nano20k_cheats_APUenhancement_20240625/README.txt

@@ -0,0 +1,9 @@
+NESTang - an FPGA NES implemented with Tang Nano 20K, Primer 25K
+
+What's new in v0.11:
+
+- Add a menu item to switch between snestang and nestang cores. Just put the .bin core files in /cores directory.
+
+See installation.pdf for instructions, including how to wire the SNES/NES controllers.
+
+Visit https://github.com/nand2mario/nestang for more instructions.

nestang_nano20k.gprj

@@ -9,6 +9,7 @@
         <File path="src/apu.v" type="file.verilog" enable="1"/>
         <File path="src/autofire.v" type="file.verilog" enable="1"/>
         <File path="src/cart.sv" type="file.verilog" enable="1"/>
+        <File path="src/cheat_wizard.v" type="file.verilog" enable="1"/>
         <File path="src/compat.v" type="file.verilog" enable="1"/>
         <File path="src/controller_ds2.sv" type="file.verilog" enable="1"/>
         <File path="src/controller_snes.v" type="file.verilog" enable="1"/>
@@ -43,6 +44,7 @@
         <File path="src/mappers/Namco.sv" type="file.verilog" enable="1"/>
         <File path="src/mappers/Sachen.sv" type="file.verilog" enable="1"/>
         <File path="src/mappers/Sunsoft.sv" type="file.verilog" enable="1"/>
+        <File path="src/mappers/VRC.sv" type="file.verilog" enable="1"/>
         <File path="src/mappers/generic.sv" type="file.verilog" enable="1"/>
         <File path="src/mappers/iir_filter.v" type="file.verilog" enable="1"/>
         <File path="src/mappers/misc.sv" type="file.verilog" enable="1"/>
@@ -61,6 +63,7 @@
         <File path="src/uart_tx_V2.v" type="file.verilog" enable="1"/>
         <File path="src/usb_hid_host.v" type="file.verilog" enable="1"/>
         <File path="src/usb_hid_host_rom.v" type="file.verilog" enable="1"/>
+        <File path="src/wishbone_slaves.vh" type="file.verilog" enable="1"/>
         <File path="src/nano20k/nestang.cst" type="file.cst" enable="1"/>
         <File path="src/nano20k/nestang.sdc" type="file.sdc" enable="1"/>
         <File path="src/nes.gao" type="file.gao" enable="0"/>

src/.gitignore

@@ -0,0 +1,9 @@
+wishbone_slave/
+wishbone_slave_bound/
+wishbone_slave_prf/
+wishbone_slave_cvr/
+
+cheat_wizard/
+cheat_wizard_bound/
+cheat_wizard_prf/
+cheat_wizard_cvr/