Using Makefile for building

Table of contents

1. Basic concepts
2. Rules
3. Variable in Makefile

Basic concepts

• 'Hello, world' makefile

hello.o: hello.c
    gcc hello.c -o hello.o

Above makefile script is to build a program 'hello.c' by using the GCC compiler. Perform the following command to build the makefile:

nhivp@nhipham:~/mcu/TM4C123_GCC_Prj/using_make/hello$ make
gcc hello.c -o hello.o

Notes:

• If no-command line targets are given, then the first target in the files is used.

Rules

A rule consists of 2 parts: the target, its prerequisites and the command to perform:

target: prereq1 prereq2
    commands

The more complete form of a rule as follows:

target1 target2 target3: prereq1 prereq2 prereq3
    command1
    command2

Variable in Makefile

A variable name must be surrounded by $(variable_name) or ${variable_name}

Automatic variable

variable	description
$@	representing the target
$<	The first prerequisite
$^	all prerequisites

Automatic Dependency Generation

Script for generating

Apply to build

Creating and updating libraries

include vs -include

The make will build with no error message if the makefile does not exist or cannot be remade.

-include filenames...

No error occurs if the filenames does exist.

Some errors with rules

• Tab character

nhivp@nhipham:~/mcu/TM4C123_GCC_Prj/using_make/rules$ make
Makefile:2: *** missing separator.  Stop.

Each command must begin with a tab character. So, you need to check the tab character at each command in the rules.

• The specified target from the command is not in the makefile. For example,

nhivp@nhipham:~/mcu/TM4C123_GCC_Prj/using_make/rules$ make hi
make: *** No rule to make target 'hi'.  Stop.

Reference

• GCC and Make - Compiling, Linking and Building C/C++ Applications
• Managing projects with GNU make