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type t = { counter : int Atomic.t; total : int } | ||
(** This barrier is designed to take a single cache line (or word) and to return | ||
with the participating domains synchronized as precisely as possible. *) | ||
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type t = int Atomic.t | ||
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let bits = (Sys.int_size - 1) / 2 | ||
let mask = (1 lsl bits) - 1 | ||
let one = 1 lsl bits | ||
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let make total = | ||
{ counter = Atomic.make 0 |> Multicore_magic.copy_as_padded; total } | ||
|> Multicore_magic.copy_as_padded | ||
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let await { counter; total } = | ||
if Atomic.get counter = total then | ||
Atomic.compare_and_set counter total 0 |> ignore; | ||
Atomic.incr counter; | ||
while Atomic.get counter < total do | ||
if total <= 0 || mask < total then invalid_arg "Barrier: out of bounds"; | ||
Atomic.make total |> Multicore_magic.copy_as_padded | ||
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let await t = | ||
let state = Atomic.fetch_and_add t one in | ||
let total = state land mask in | ||
if state lsr bits = total - 1 then Atomic.set t (total - (total lsl bits)); | ||
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while 0 < Atomic.get t do | ||
Domain.cpu_relax () | ||
done; | ||
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Atomic.fetch_and_add t one |> ignore; | ||
while Atomic.get t < 0 do | ||
Domain.cpu_relax () | ||
done |
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