AES Implementation in Verilog

AesMain.v

@@ -0,0 +1,25 @@
+module AesMain(din, key, dout);
+
+    input [127:0] din;
+    input [127:0] key;
+    output[127:0] dout;
+
+    wire [127:0] out0, out1, out2, out3, out4, out5, out6, out7, out8, out9;
+
+    wire [127:0] kout1, kout2, kout3, kout4, kout5, kout6, kout7, kout8, kout9;
+
+	assign out0 = din^key;
+
+    Round r1(.rc(4'b0000), .data(out0), .kin(key), .kout(kout1), .rndout(out1));
+    Round r2(.rc(4'b0001), .data(out1), .kin(kout1), .kout(kout2), .rndout(out2));
+    Round r3(.rc(4'b0010), .data(out2), .kin(kout2), .kout(kout3), .rndout(out3));
+    Round r4(.rc(4'b0011), .data(out3), .kin(kout3), .kout(kout4), .rndout(out4));
+    Round r5(.rc(4'b0100), .data(out4), .kin(kout4), .kout(kout5), .rndout(out5));
+    Round r6(.rc(4'b0101), .data(out5), .kin(kout5), .kout(kout6), .rndout(out6));
+    Round r7(.rc(4'b0110), .data(out6), .kin(kout6), .kout(kout7), .rndout(out7));
+    Round r8(.rc(4'b0111), .data(out7), .kin(kout7), .kout(kout8), .rndout(out8));
+    Round r9(.rc(4'b1000), .data(out8), .kin(kout8), .kout(kout9), .rndout(out9));
+
+    Round_final r10(.rc(4'b1001), .rin(out9), .kin(kout9), .fout(dout));
+
+endmodule

AesMain.v.bak

@@ -0,0 +1,26 @@
+module AesMain(din, key, dout);
+
+    input clk;
+    input [127:0] din;
+    input [127:0] key;
+    output[127:0] dout;
+
+    wire [127:0] out0, out1, out2, out3, out4, out5, out6, out7, out8, out9;
+
+    wire [127:0] kout1, kout2, kout3, kout4, kout5, kout6, kout7, kout8, kout9;
+
+	assign out0 = din^key;
+
+    Round r1(.rc(4'b0000), .data(out0), .kin(key), .kout(kout1), .rndout(out1));
+    Round r2(.rc(4'b0001), .data(out1), .kin(kout1), .kout(kout2), .rndout(out2));
+    Round r3(.rc(4'b0010), .data(out2), .kin(kout2), .kout(kout3), .rndout(out3));
+    Round r4(.rc(4'b0011), .data(out3), .kin(kout3), .kout(kout4), .rndout(out4));
+    Round r5(.rc(4'b0100), .data(out4), .kin(kout4), .kout(kout5), .rndout(out5));
+    Round r6(.rc(4'b0101), .data(out5), .kin(kout5), .kout(kout6), .rndout(out6));
+    Round r7(.rc(4'b0110), .data(out6), .kin(kout6), .kout(kout7), .rndout(out7));
+    Round r8(.rc(4'b0111), .data(out7), .kin(kout7), .kout(kout8), .rndout(out8));
+    Round r9(.rc(4'b1000), .data(out8), .kin(kout8), .kout(kout9), .rndout(out9));
+
+    Round_final r10(.rc(4'b1001), .rin(out9), .kin(kout9), .fout(dout));
+
+endmodule

Input.txt

@@ -0,0 +1,10 @@
+000000003847e567a6f7778c8ea567a4
+000000003847e567a6f7778c8ea567a4
+a31435dcea435ddde673abc446aacd12
+9999aacbd3425acd341325dcae564de3
+468723ace132426dcf6a6cd6e738afcd
+5afa9844de45740987bcdef755437889
+fafae75747647bbcbcbcbc76565675ea
+876868a76aba67a6a6adaea53132cd97
+7574232689794245546babaecbabaeff
+1356789757556baeefffaddae73da544

Key.txt

@@ -0,0 +1,10 @@
+00000003a45ed56ff45cc5d43456aad6
+34dc1789be564123cd58ca564288ac51
+6178000acd748cdaeea657468ccaed65
+0000035645aacde342dcae235346eca5
+928eacdf78f742f2fafafa456575656a
+7827532558398312631536bbababfefe
+27612443643238983023562576893abc
+dbacdfebacefefdca237126323687693
+abcfdedafacbfe728293a3829264bac7
+53673128936328174abacdeefeda8736

KeyGen.v

@@ -0,0 +1,43 @@
+module KeyGen(rc, kin, kout);
+
+    input [3:0] rc;
+    input [127:0] kin;
+    output [127:0] kout;
+
+    wire [31:0] w0, w1, w2, w3, tem;
+
+    assign w0 = kin[31:0];
+    assign w1 = kin[63:32];
+    assign w2 = kin[95:64];
+    assign w3 = kin[127:96];
+
+    assign kout[31:0]   = w3 ^ tem ^ rcon(rc) ^ w2 ^ w1 ^ w0;
+    assign kout[63:32]  = w3 ^ tem ^ rcon(rc) ^ w2 ^ w1;
+    assign kout[95:64]  = w3 ^ tem ^ rcon(rc) ^ w2;   
+    assign kout[127:96] = w3 ^ tem ^ rcon(rc);
+
+    SBox a1(.in(w0[23:16]), .out(tem[31:24]));
+    SBox a2(.in(w0[15:8]), .out(tem[23:16]));
+    SBox a3(.in(w0[7:0]), .out(tem[15:8]));
+    SBox a4(.in(w0[31:24]), .out(tem[7:0]));
+
+    function [31:0]	rcon;
+
+      input	[3:0]	rc;
+      case(rc)	
+         4'h0: rcon=32'h01_00_00_00;
+         4'h1: rcon=32'h02_00_00_00;
+         4'h2: rcon=32'h04_00_00_00;
+         4'h3: rcon=32'h08_00_00_00;
+         4'h4: rcon=32'h10_00_00_00;
+         4'h5: rcon=32'h20_00_00_00;
+         4'h6: rcon=32'h40_00_00_00;
+         4'h7: rcon=32'h80_00_00_00;
+         4'h8: rcon=32'h1b_00_00_00;
+         4'h9: rcon=32'h36_00_00_00;
+         default: rcon=32'h00_00_00_00;
+       endcase
+
+    endfunction
+
+endmodule

KeyGen.v.bak

@@ -0,0 +1,43 @@
+module KeyGen(rc, kin, kout);
+
+    input [3:0] rc;
+    input [127:0] kin;
+    output [127:0] kout;
+
+    wire [31:0] w0, w1, w2, w3, tem;
+
+    assign w0 = kin[31:0];
+    assign w1 = kin[63:32];
+    assign w2 = kin[95:64];
+    assign w3 = kin[127:96];
+
+    assign kout[31:0]   = w3 ^ tem ^ rcon(rc) ^ w2 ^ w1 ^ w0;
+    assign kout[63:32]  = w3 ^ tem ^ rcon(rc) ^ w2 ^ w1;
+    assign kout[95:64]  = w3 ^ tem ^ rcon(rc) ^ w2;   
+    assign kout[127:96] = w3 ^ tem ^ rcon(rc);
+
+    Sbox a1(.a(w0[23:16]), .c(tem[31:24]));
+    Sbox a2(.a(w0[15:8]), .c(tem[23:16]));
+    Sbox a3(.a(w0[7:0]), .c(tem[15:8]));
+    Sbox a4(.a(w0[31:24]), .c(tem[7:0]));
+
+    function [31:0]	rcon;
+
+      input	[3:0]	rc;
+      case(rc)	
+         4'h0: rcon=32'h01_00_00_00;
+         4'h1: rcon=32'h02_00_00_00;
+         4'h2: rcon=32'h04_00_00_00;
+         4'h3: rcon=32'h08_00_00_00;
+         4'h4: rcon=32'h10_00_00_00;
+         4'h5: rcon=32'h20_00_00_00;
+         4'h6: rcon=32'h40_00_00_00;
+         4'h7: rcon=32'h80_00_00_00;
+         4'h8: rcon=32'h1b_00_00_00;
+         4'h9: rcon=32'h36_00_00_00;
+         default: rcon=32'h00_00_00_00;
+       endcase
+
+    endfunction
+
+endmodule

MixColumn.v

@@ -0,0 +1,47 @@
+//after changing the state using ShiftRow Module we use MixCol method
+
+module MixColumn(stateR, stateM);
+
+input [127:0] stateR;
+output [127:0] stateM;
+
+mixCol m0(stateR[7:0], stateR[31:24], stateR[23:16], stateR[15:8], stateM[7:0]);
+mixCol m1(stateR[39:32], stateR[63:56], stateR[55:48], stateR[47:40], stateM[39:32]);
+mixCol m2(stateR[71:64], stateR[95:88], stateR[87:80], stateR[79:72], stateM[71:64]);
+mixCol m3(stateR[103:96], stateR[127:120], stateR[119:112], stateR[111:104], stateM[103:96]);
+
+mixCol m4(stateR[15:8], stateR[7:0], stateR[31:24], stateR[23:16], stateM[15:8]);
+mixCol m5(stateR[47:40], stateR[39:32], stateR[63:56], stateR[55:48], stateM[47:40]);
+mixCol m6(stateR[79:72], stateR[71:64], stateR[95:88], stateR[87:80], stateM[79:72]);
+mixCol m7(stateR[111:104], stateR[103:96], stateR[127:120], stateR[119:112], stateM[111:104]);
+
+mixCol m8(stateR[23:16], stateR[15:8], stateR[7:0], stateR[31:24], stateM[23:16]);
+mixCol m9(stateR[55:48], stateR[47:40], stateR[39:32], stateR[63:56], stateM[55:48]);
+mixCol m10(stateR[87:80], stateR[79:72], stateR[71:64], stateR[95:88], stateM[87:80]);
+mixCol m11(stateR[119:112], stateR[111:104], stateR[103:96], stateR[127:120], stateM[119:112]);
+
+mixCol m12(stateR[31:24], stateR[23:16], stateR[15:8], stateR[7:0], stateM[31:24]);
+mixCol m13(stateR[63:56], stateR[55:48], stateR[47:40], stateR[39:32], stateM[63:56]);
+mixCol m14(stateR[95:88], stateR[87:80], stateR[79:72], stateR[71:64], stateM[95:88]);
+mixCol m15(stateR[127:120], stateR[119:112], stateR[111:104], stateR[103:96], stateM[127:120]);
+
+endmodule
+
+
+//mix module which uses the mixColumn matrix derivedinpn theory to change state
+
+module mixCol(inp1, inp2, inp3, inp4, mix);
+
+input [7:0]inp1, inp2, inp3, inp4;
+output [7:0]mix;
+
+assign mix[0] = inp1[7] ^ inp2[7] ^ inp2[0] ^ inp3[0] ^ inp4[0];
+assign mix[1] = inp1[0] ^ inp1[7] ^ inp2[0] ^ inp2[1] ^ inp2[7] ^ inp3[1] ^ inp4[1];
+assign mix[2] = inp1[1] ^ inp2[1] ^ inp2[2] ^ inp3[2] ^ inp4[2];
+assign mix[3] = inp1[2] ^ inp1[7] ^ inp2[2] ^ inp2[3] ^ inp2[7] ^ inp3[3] ^ inp4[3];
+assign mix[4] = inp1[3] ^ inp1[7] ^ inp2[3] ^ inp2[4] ^ inp2[7] ^ inp3[4] ^ inp4[4];
+assign mix[5] = inp1[4] ^ inp2[4] ^ inp2[5] ^ inp3[5] ^ inp4[5];
+assign mix[6] = inp1[5] ^ inp2[5] ^ inp2[6] ^ inp3[6] ^ inp4[6];
+assign mix[7] = inp1[6] ^ inp2[6] ^ inp2[7] ^ inp3[7] ^ inp4[7];
+
+endmodule

Output.txt

@@ -0,0 +1,10 @@
+0ec0bd1f118a1b7d6ffbf83cb41bd026
+bae64c2b8df8303686170411c0db78bc
+ddccda998960f17e3e5c344d3af3cbcf
+b97291b67a227f4b090422be9c0b22e2
+c06f5000d6acc7ece33f4fef20ff6e2d
+9871e7c49cd433c851669a862a2bfc4c
+bf8dd9e1e693a4f6cf35dcdbdbf8a2ac
+cc92ea3436ff651e9c140f9a24e69e73
+f1e88f6340b9a82e708fc99f76ebb15b
+05495a544d04250d41821dfbe5f897c1

Rounds.v

@@ -0,0 +1,35 @@
+//first 9 Rounds
+module Round(rc, data, kin, kout, rndout);
+
+input [3:0]rc;
+input [127:0]data;
+input [127:0]kin;
+output [127:0]kout;
+output [127:0]rndout;
+
+wire [127:0] sb, sr, mcl;
+
+KeyGen t0(.rc(rc), .kin(kin), .kout(kout));
+SubBytes t1(.stateIn(data), .stateOut(sb));
+ShiftRows t2(.stateB(sb), .stateR(sr));
+MixColumn t3(.stateR(sr), .stateM(mcl));
+assign rndout= kout^mcl;
+
+endmodule
+
+//final Round
+module Round_final(rc, rin, kin, fout);
+
+input [3:0]rc;
+input [127:0]rin;
+input [127:0]kin;
+output [127:0]fout;
+
+wire [127:0] sb, sr, mcl, kout;
+
+KeyGen t0(.rc(rc), .kin(kin), .kout(kout));
+SubBytes t1(.stateIn(rin), .stateOut(sb));
+ShiftRows t2(.stateB(sb), .stateR(sr));
+assign fout= kout^sr;
+
+endmodule