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[CUDA] Report that devices with cc >= sm_70 support seq_cst #1291
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LGTM! 🥳
Btw, small aside, I think at some point it may be good we cache stuff like CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR
in the device on init, as we seem to use it for a bunch of device cap queries, so while not much it may be useful to remove the overhead (or rather move it to a one-time on init).
I've also now marked fence seq_cst supported by sm70. This is already the situation in the latest intel/llvm, see intel/llvm#12713 for a description. |
Please pull in the main branch to have up to date testing, also update the tag in the intel/llvm PR. |
cuda ptx 6.0 memory consistency model is implemented in dpc++ for devices > sm_70. Signed-off-by: JackAKirk <jack.kirk@codeplay.com>
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Codecov ReportAll modified and coverable lines are covered by tests ✅
❗ Your organization needs to install the Codecov GitHub app to enable full functionality. Additional details and impacted files@@ Coverage Diff @@
## main #1291 +/- ##
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- Coverage 15.46% 12.49% -2.98%
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Files 238 239 +1
Lines 33883 36003 +2120
Branches 3747 4086 +339
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- Hits 5240 4498 -742
- Misses 28593 31501 +2908
+ Partials 50 4 -46 ☔ View full report in Codecov by Sentry. |
Report that devices with cc >= sm_70 support seq_cst memory consistency capabilities. Tested with intel/llvm#12516