Fix BSCAN placement, use openXC7 metadata

Details: https://github.com/openXC7/nextpnr-xilinx/releases/tag/0.8.2

Fix broken BRAMs, DRIVE attribute

Details:
https://github.com/openXC7/nextpnr-xilinx/releases/tag/0.8.1

GTP support

Release changes see:
https://github.com/openXC7/nextpnr-xilinx/releases/tag/0.8.0

MMCME2_ADV support, OSERDESE2 fixes, better error messages

This release

• Adds support for the MMCME2_ADV primitive. Integer and fractional scaling has been tested. Dynamic reconfiguration ports have been implemented, but not tested (yet). Please let me know, if you have tried those.
• Fixes issues in OSERDESE2 (use of the OFB port was not possible)
• Better error messages (especially if the chip database is out of date)

Bugfix release: Backport to stable codebase

Using the latest upstream codebase unfortunately prevented us using router2,
which is often many times faster than router1.
Router2 now is the default router again.
Also some designs stopped working, because the timing of router2 is better.
This release backports all the latest changes on the old, stable codebase,
giving you the best stability and performance.
Further development will be made to both branches,
until the upstream branches' router2 issues (like endless loops),
will be solved.

Implement CFG_CENTER primitives: STARTUPE2, BSCANE2, ICAPE2, DCIRESET, DNA_PORT, EFUSE_USR, FRAME_ECCE2, USR_ACCESSE2

The following new primitives of the CFG_CENTER_* tiles are now supported:

• STARTUPE2
• BSCANE2
• ICAPE2
• DCIRESET
• DNA_PORT
• EFUSE_USR
• FRAME_ECCE2
• USR_ACCESSE2

Only STARTUPE2 and BSCANE2 have been tested on hardware so far.
Please let me know if you have issues.

Bugfix release: OE line inverted on bidirectional IOs

This fixes a critical bug where the output enable line is inverted on bidirectional IOs.
This only surfaces with router1, but since router2 is currently not reliable due to
the upstream backport, this is the current default choice.

Support negedge blocks, add TMDS_33 support, fix LVDS_25

Changes:

• negative edge flip-flops are supported now, which is important for always(@Negedge ..) blocks
• TMDS_33 IO standard is now supported (important for HDMI)
• bugfix for LVDS_25 IO standard

DSP48E1 support, Spartan7 support

• Support DSP48E1 hardware multipliers, including cascaded hardware multipliers. It is not feature complete, but now should handle most of portable verilog that is inferred by Yosys.
• Added Spartan7 support
• Now router1 is the default router, because router2 has problems routing DSP blocks. It still might work on some designs, though.

Support for IDDR, ODDR, ODELAYE2 primitives

Support for the IDDR and ODDR primitives has been added.
With this release, it is now possible to have DDR3 memory with output
delay calibration (ODELAYE2 primitive, tested with the LiteX K7DDRPHY).
Those primitives are not feature complete, but support the most important
use cases.

       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Jan 24 2023 08:30:11
 BIOS CRC passed (24afd96f)

 LiteX git sha1: 8b14e649

--=============== SoC ==================--
CPU:		VexRiscv_Min @ 100MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB
SDRAM:		4.0GiB 16-bit @ 800MT/s (CL-6 CWL-5)
MAIN-RAM:	256.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
  tCK equivalent taps: 32
  Cmd/Clk scan (0-16)
  |1111111111110000| best: 0
  Setting Cmd/Clk delay to 0 taps.
  Data scan:
  m0: |000000000011111111111111| delay: 10
  m1: |000000000011111111111111| delay: 10
Write latency calibration:
m0:0 m1:0 
Write DQ-DQS training:
m0: |000011111111111111000000000000000| delays: 10+-06
m1: |000111111111111111100000000000000| delays: 10+-07
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |00000000000000000000000000000000| delays: -
  m0, b02: |01111111111110000000000000000000| delays: 07+-04
  m0, b03: |00000000000000011111111111111000| delays: 21+-05
  m0, b04: |00000000000000000000000000000000| delays: 30+-00
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00000000000000000000000000000000| delays: -
  m0, b07: |00000000000000000000000000000000| delays: -
  best: m0, b03 delays: 21+-05
  m1, b00: |00000000000000000000000000000000| delays: -
  m1, b01: |00000000000000000000000000000000| delays: 00+-00
  m1, b02: |00110111111111001000000000000000| delays: 09+-06
  m1, b03: |00000000000000000101111111111111| delays: 24+-06
  m1, b04: |00000000000000000000000000000000| delays: -
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |00000000000000000000000000000000| delays: -
  m1, b07: |00000000000000000000000000000000| delays: -
  best: m1, b03 delays: 24+-05
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB     
   Read: 0x40000000-0x40200000 2.0MiB     
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 72.5MiB/s
   Read speed: 26.1MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
             Timeout
No boot medium found

--============= Console ================--

litex> mem_list
Available memory regions:
ROM       0x00000000 0x20000 
SRAM      0x10000000 0x2000 
MAIN_RAM  0x40000000 0x10000000 
CSR       0xf0000000 0x10000 

litex> mem_test 0x40000000 0x10000000 
Memtest at 0x40000000 (256.0MiB)...
  Write: 0x40000000-0x50000000 256.0MiB   
   Read: 0x40000000-0x50000000 256.0MiB   
Memtest OK