Skip to content

Commit

Permalink
remove dead code
Browse files Browse the repository at this point in the history
  • Loading branch information
alexkeizer committed Sep 24, 2024
1 parent decf9df commit df8887e
Showing 1 changed file with 0 additions and 10 deletions.
10 changes: 0 additions & 10 deletions src/Init/Data/BitVec/Bitblast.lean
Original file line number Diff line number Diff line change
Expand Up @@ -621,10 +621,6 @@ theorem DivModState.umod_eq_of_lawful {qr : DivModState w}

/-! ### DivModState.Poised -/

/-
TODO: Can we redefine `qr.Poised` as simply `¬qr.IsFinal`?
That would mean we have extra `Lawful` assumptions in some spots, but in others we'll have less,
as we won't have to carry around the `args` -/
/--
A `Poised` DivModState is a state which is `Lawful` and furthermore, has at least
one numerator bit left to process `(0 < wn)`
Expand All @@ -646,12 +642,6 @@ def DivModState.wr_lt_w {qr : DivModState w} (h : qr.Poised args) : qr.wr < w :=
have hwn_lt := h.hwn_lt
omega

-- /-- If we have extra bits to spare in `n`,
-- then we know the div mod state is poised to run another round of the shift subtractor. -/
-- def DivModState.Lawful.toPoised {qr : DivModState w}
-- (h : qr.Lawful w wr (wn + 1) n d) : qr.Poised wr (wn + 1) n d :=
-- { h with hwn_lt := by omega }

/-! ### Division shift subtractor -/

/--
Expand Down

0 comments on commit df8887e

Please sign in to comment.