Merge pull request #143 from openrisc/licence-switch-cern-ohl-v2-w

Licence switch OHDL to CERN OHL-W V2
openrisc · Jan 9, 2022 · ff11d2c · ff11d2c
2 parents 95eee05 + c666fde
commit ff11d2c
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diff --git a/LICENSE b/LICENSE
diff --git a/README.md b/README.md
@@ -22,8 +22,12 @@ build the HTML documentation, run the following in the [doc/](doc/) directory:
 
 ## License
 
-This project is licensed under the Open Hardware Description License (OHDL). For
-details please see the [LICENSE](./LICENSE) file or http://juliusbaxter.net/ohdl/
+This project is licensed under the CERN Open Hardware Licence Version 2 - Weakly Reciprocal (CERN-OHL-W). For
+details please see the [LICENSE](./LICENSE) file or https:/cern.ch/cern-ohl
+
+SPDX-License-Identifier: CERN-OHL-W-2.0
+
+https://spdx.org/licenses/CERN-OHL-W-2.0.html
 
 ## Configuration
 

diff --git a/bench/formal/Makefile b/bench/formal/Makefile
@@ -1,8 +1,5 @@
 ###########################################################
-# This Source Code Form is subject to the terms of the
-# Open Hardware Description License, v. 1.0. If a copy
-# of the OHDL was not distributed with this file, You
-# can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+# SPDX-License-Identifier: CERN-OHL-W-2.0
 #
 # Description: Simplistic makefile for running formal tests
 #

diff --git a/bench/formal/f_multiclock_op.v b/bench/formal/f_multiclock_op.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx formal multiclock alu operation checker
 

diff --git a/bench/formal/fspr_master.v b/bench/formal/fspr_master.v
@@ -1,4 +1,8 @@
-module fspr_master
+/* ****************************************************************************
+  SPDX-License-Identifier: CERN-OHL-W-2.0
+  ***************************************************************************** */
+
+ module fspr_master
 #(
   parameter OPTION_OPERAND_WIDTH = 32
   )

diff --git a/bench/formal/fspr_slave.v b/bench/formal/fspr_slave.v
@@ -1,3 +1,7 @@
+/* ****************************************************************************
+  SPDX-License-Identifier: CERN-OHL-W-2.0
+  ***************************************************************************** */
+
 module fspr_slave
 #(
   parameter OPTION_OPERAND_WIDTH = 32,

diff --git a/bench/verilog/mor1kx_monitor.v b/bench/verilog/mor1kx_monitor.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the 
-  Open Hardware Description License, v. 1.0. If a copy 
-  of the OHDL was not distributed with this file, You 
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx monitor module
  

diff --git a/bench/verilog/mor1kx_traceport_monitor.v b/bench/verilog/mor1kx_traceport_monitor.v
@@ -1,3 +1,7 @@
+/* ****************************************************************************
+  SPDX-License-Identifier: CERN-OHL-W-2.0
+***************************************************************************** */
+
 `include "mor1kx-defines.v"
 
 `define OR1K_OPCODE_POS 31:26

diff --git a/rtl/verilog/mor1kx-defines.v b/rtl/verilog/mor1kx-defines.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx defines
 

diff --git a/rtl/verilog/mor1kx-sprs.v b/rtl/verilog/mor1kx-sprs.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: SPR definitions
 

diff --git a/rtl/verilog/mor1kx.v b/rtl/verilog/mor1kx.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx processor top level
 

diff --git a/rtl/verilog/mor1kx_branch_prediction.v b/rtl/verilog/mor1kx_branch_prediction.v
@@ -1,17 +1,14 @@
-/******************************************************************************
- This Source Code Form is subject to the terms of the
- Open Hardware Description License, v. 1.0. If a copy
- of the OHDL was not distributed with this file, You
- can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+/* ****************************************************************************
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
- Description: Branch prediction module
- Generates a predicted flag output and compares that to the real flag
- when it comes back in the following pipeline stage.
- Signals are deliberately not named after the pipeline stage they belong to,
- in order to keep this module generic.
+  Description: Branch prediction module
+  Generates a predicted flag output and compares that to the real flag
+  when it comes back in the following pipeline stage.
+  Signals are deliberately not named after the pipeline stage they belong to,
+  in order to keep this module generic.
 
- Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- Copyright (C) 2016 Alexey Baturo <baturo.alexey@gmail.com>
+  Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+  Copyright (C) 2016 Alexey Baturo <baturo.alexey@gmail.com>
 
  ******************************************************************************/
 

diff --git a/rtl/verilog/mor1kx_branch_predictor_gshare.v b/rtl/verilog/mor1kx_branch_predictor_gshare.v
@@ -1,15 +1,12 @@
-/******************************************************************************
- This Source Code Form is subject to the terms of the
- Open Hardware Description License, v. 1.0. If a copy
- of the OHDL was not distributed with this file, You
- can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
-
- Description: gshare branch predictor
- This predictor is based on array of FSMs with 4 states: strongly not taken,
- weakly not taken, weakly taken, strongly taken. Check saturation predictor.
- Index to the array of FSMs is built using xor of global history and lower bits of PC.
-
- Copyright (C) 2016 Alexey Baturo <baturo.alexey@gmail.com>
+/* ****************************************************************************
+  SPDX-License-Identifier: CERN-OHL-W-2.0
+
+  Description: gshare branch predictor
+  This predictor is based on array of FSMs with 4 states: strongly not taken,
+  weakly not taken, weakly taken, strongly taken. Check saturation predictor.
+  Index to the array of FSMs is built using xor of global history and lower bits of PC.
+
+  Copyright (C) 2016 Alexey Baturo <baturo.alexey@gmail.com>
 
  ******************************************************************************/
 

diff --git a/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v b/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v
@@ -1,22 +1,19 @@
-/******************************************************************************
- This Source Code Form is subject to the terms of the
- Open Hardware Description License, v. 1.0. If a copy
- of the OHDL was not distributed with this file, You
- can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+/* ****************************************************************************
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
- Description: Saturating counter branch predictor
- This is FSM with 4 states: strongly not taken, weakly not taken,
- weakly taken, strongly taken.
- Fsm changes it state upon real(not predicted) flag.
- If flag was "true" and instruction was bf  or flag was "false" and
- instruction was bnf fsm changes its state towards "taken". And vice versa
- otherwise.
- We predict flag on current fsm state and current branch type.
- If we are in any "taken" state and current instruction is bf,
- we predict flag to be "true". Or we're in any "not taken" state and
- current instruction is bnf, we predict flag to be "true".
+  Description: Saturating counter branch predictor
+  This is FSM with 4 states: strongly not taken, weakly not taken,
+  weakly taken, strongly taken.
+  Fsm changes it state upon real(not predicted) flag.
+  If flag was "true" and instruction was bf  or flag was "false" and
+  instruction was bnf fsm changes its state towards "taken". And vice versa
+  otherwise.
+  We predict flag on current fsm state and current branch type.
+  If we are in any "taken" state and current instruction is bf,
+  we predict flag to be "true". Or we're in any "not taken" state and
+  current instruction is bnf, we predict flag to be "true".
 
- Copyright (C) 2016 Alexey Baturo <baturo.alexey@gmail.com>
+  Copyright (C) 2016 Alexey Baturo <baturo.alexey@gmail.com>
 
  ******************************************************************************/
 

diff --git a/rtl/verilog/mor1kx_branch_predictor_simple.v b/rtl/verilog/mor1kx_branch_predictor_simple.v
@@ -1,14 +1,11 @@
-/******************************************************************************
- This Source Code Form is subject to the terms of the
- Open Hardware Description License, v. 1.0. If a copy
- of the OHDL was not distributed with this file, You
- can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+/* ****************************************************************************
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
- Description: Simple branch predictor implementation
- We assume flag to be "true" if instruction is bf and it jumps backwords
- or if instruction is bnf and it jumps forward.
+  Description: Simple branch predictor implementation
+  We assume flag to be "true" if instruction is bf and it jumps backwords
+  or if instruction is bnf and it jumps forward.
 
- Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+  Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 
  ******************************************************************************/
 

diff --git a/rtl/verilog/mor1kx_bus_if_wb32.v b/rtl/verilog/mor1kx_bus_if_wb32.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx processor Wishbone bus bridge
 

diff --git a/rtl/verilog/mor1kx_cache_lru.v b/rtl/verilog/mor1kx_cache_lru.v
@@ -1,12 +1,9 @@
-/******************************************************************************
- This Source Code Form is subject to the terms of the
- Open Hardware Description License, v. 1.0. If a copy
- of the OHDL was not distributed with this file, You
- can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+/* ****************************************************************************
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
- Description: Data cache LRU implementation
+  Description: Data cache LRU implementation
 
- Copyright (C) 2012 Stefan Wallentowitz <stefan.wallentowitz@tum.de>
+  Copyright (C) 2012 Stefan Wallentowitz <stefan.wallentowitz@tum.de>
 
  ******************************************************************************/
 

diff --git a/rtl/verilog/mor1kx_cfgrs.v b/rtl/verilog/mor1kx_cfgrs.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx SPRs indicating configuration and version
 

diff --git a/rtl/verilog/mor1kx_cpu.v b/rtl/verilog/mor1kx_cpu.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: CPU wrapper module
 

diff --git a/rtl/verilog/mor1kx_cpu_cappuccino.v b/rtl/verilog/mor1kx_cpu_cappuccino.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: "Cappuccino" pipeline CPU module
 

diff --git a/rtl/verilog/mor1kx_cpu_espresso.v b/rtl/verilog/mor1kx_cpu_espresso.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: Espresso pipeline CPU module
 

diff --git a/rtl/verilog/mor1kx_cpu_prontoespresso.v b/rtl/verilog/mor1kx_cpu_prontoespresso.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: "Pronto espresso" pipeline CPU module
 

diff --git a/rtl/verilog/mor1kx_ctrl_cappuccino.v b/rtl/verilog/mor1kx_ctrl_cappuccino.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx control unit
 

diff --git a/rtl/verilog/mor1kx_ctrl_espresso.v b/rtl/verilog/mor1kx_ctrl_espresso.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx espresso pipeline control unit
 

diff --git a/rtl/verilog/mor1kx_ctrl_prontoespresso.v b/rtl/verilog/mor1kx_ctrl_prontoespresso.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx pronto espresso pipeline control unit
 

diff --git a/rtl/verilog/mor1kx_dcache.v b/rtl/verilog/mor1kx_dcache.v
@@ -1,14 +1,11 @@
-/******************************************************************************
- This Source Code Form is subject to the terms of the
- Open Hardware Description License, v. 1.0. If a copy
- of the OHDL was not distributed with this file, You
- can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+/* ****************************************************************************
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
- Description: Data cache implementation
+  Description: Data cache implementation
 
- Copyright (C) 2012-2013
-    Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-    Stefan Wallentowitz <stefan.wallentowitz@tum.de>
+  Copyright (C) 2012-2013
+     Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+     Stefan Wallentowitz <stefan.wallentowitz@tum.de>
 
  ******************************************************************************/
 

diff --git a/rtl/verilog/mor1kx_decode.v b/rtl/verilog/mor1kx_decode.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx decode unit
 

diff --git a/rtl/verilog/mor1kx_decode_execute_cappuccino.v b/rtl/verilog/mor1kx_decode_execute_cappuccino.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: Cappuccino decode to execute module.
   - Decode to execute stage signal passing.

diff --git a/rtl/verilog/mor1kx_dmmu.v b/rtl/verilog/mor1kx_dmmu.v
@@ -1,12 +1,9 @@
-/******************************************************************************
- This Source Code Form is subject to the terms of the
- Open Hardware Description License, v. 1.0. If a copy
- of the OHDL was not distributed with this file, You
- can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+/* ****************************************************************************
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
- Description: Data MMU implementation
+  Description: Data MMU implementation
 
- Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+  Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 
  ******************************************************************************/
 

diff --git a/rtl/verilog/mor1kx_execute_alu.v b/rtl/verilog/mor1kx_execute_alu.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: mor1kx execute stage ALU
 

diff --git a/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v b/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v
@@ -1,8 +1,5 @@
 /* ****************************************************************************
-  This Source Code Form is subject to the terms of the
-  Open Hardware Description License, v. 1.0. If a copy
-  of the OHDL was not distributed with this file, You
-  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+  SPDX-License-Identifier: CERN-OHL-W-2.0
 
   Description: execute to control stage signal passing