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feat: update BitwiseOperationLookupAir_8 for openvm v2.0.0-rc.1#30

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Tuanlinh12312 wants to merge 3 commits intodevelop-v2.0.0from
feat/INT-6543-bitwise-op-lookup
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feat: update BitwiseOperationLookupAir_8 for openvm v2.0.0-rc.1#30
Tuanlinh12312 wants to merge 3 commits intodevelop-v2.0.0from
feat/INT-6543-bitwise-op-lookup

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@Tuanlinh12312 Tuanlinh12312 commented Mar 4, 2026

Resolves INT-6543.

Overview

Update BitwiseOperationLookupAir_8 for the OpenVM v2.0.0-rc.1 layout, prove its bus well-formedness properties, and align its interaction wiring with the repo’s BitwiseBus.

Code Changes

OpenvmFv/Airs/BitwiseOperationLookupAir_8.lean, OpenvmFv/Extraction/BitwiseOperationLookupAir_8.lean

  • add the AIR/extraction pipeline for BitwiseOperationLookupAir_8
  • model the chip with 18 main columns:
    x_bits_0..7, y_bits_0..7, mult_range, mult_xor
  • add the extracted booleanity, transition, first-row, and last-row constraints for the rc.1 layout
  • route the bitwise interactions to BitwiseBus
  • emit the two per-row bus entries:
    • range-check entry: [x, y, 0, 0]
    • xor entry: [x, y, xor, 1]

OpenvmFv/Constraints/BitwiseOperationLookupAir_8.lean

  • add the simplified constraint layer for the extracted AIR
  • add the allHold / allHold_simplified infrastructure
  • prove booleanity of all bit columns
  • reconstruct x, y, and xor from the bit columns
  • prove the range properties x.val < 256 and y.val < 256
  • prove the XOR correctness property for the second emitted bus entry
  • prove the two row-level well-formedness theorems:
    • wf_properties_range
    • wf_properties_xor
  • add two iff lemmas connecting those theorems to Interaction.BitwiseBusEntryInstance.wf_properties
  • align the simplified interaction statement with BitwiseBus instead of the stale bus 6

Hypotheses

The final well-formedness theorems assume:

  • all_constraints_hold air: the extracted/simplified constraints hold at every valid row
  • row ≤ air.last_row: the theorem is stated only for valid trace rows

No additional rotation-consistency or field-size hypothesis is needed for this proof.

Verification

  • lake build OpenvmFv.Constraints.BitwiseOperationLookupAir_8 OpenvmFv.Equivalence.BaseALU OpenvmFv.Equivalence.Mulh OpenvmFv.Equivalence.DivRem

@Tuanlinh12312 Tuanlinh12312 force-pushed the feat/INT-6543-bitwise-op-lookup branch from d290287 to 37a03f1 Compare March 5, 2026 18:36
Base automatically changed from feat/INT-6541-extractor to develop-v2.0.0 March 10, 2026 15:14
Tuanlinh12312 and others added 3 commits March 10, 2026 19:56
Replace old preprocessed-column-based BitwiseOperationLookupAir with new
gate-based binary decomposition version. Old: 3 preprocessed + 2 main cols,
no constraints. New: 18 main cols (8 x_bits + 8 y_bits + mult_range +
mult_xor), 19 polynomial constraints, bus 6.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Prove that the 19 polynomial constraints imply
BitwiseBusEntryInstance.wf_properties for both bus entries
(range-check and XOR). 11 lemmas in 3 phases:

- Phase A: bits_boolean (constraints 0-15 → boolean bit columns)
- Phase B: binary_sum_lt_256, x_val_lt_256, y_val_lt_256
- Phase C: bit_xor_val, bit_xor_boolean, binary_sum_val_eq,
  nat_xor_binary_decomp, binary_xor_sum_correct

The XOR correctness proof uses a compositional approach:
lift Fin.val through arithmetic, convert per-bit XOR via
a+b-2ab identity, then apply Nat.xor binary decomposition
(proved over Fin 2 for decidability via native_decide).

Co-Authored-By: Aristotle (Harmonic) <aristotle-harmonic@harmonic.fun>
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
@Tuanlinh12312 Tuanlinh12312 force-pushed the feat/INT-6543-bitwise-op-lookup branch from 2bcbee5 to 16c5b95 Compare March 10, 2026 20:49
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