feat: update BitwiseOperationLookupAir_8 for openvm v2.0.0-rc.1#30
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Tuanlinh12312 wants to merge 3 commits intodevelop-v2.0.0from
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feat: update BitwiseOperationLookupAir_8 for openvm v2.0.0-rc.1#30Tuanlinh12312 wants to merge 3 commits intodevelop-v2.0.0from
Tuanlinh12312 wants to merge 3 commits intodevelop-v2.0.0from
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Replace old preprocessed-column-based BitwiseOperationLookupAir with new gate-based binary decomposition version. Old: 3 preprocessed + 2 main cols, no constraints. New: 18 main cols (8 x_bits + 8 y_bits + mult_range + mult_xor), 19 polynomial constraints, bus 6. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Prove that the 19 polynomial constraints imply BitwiseBusEntryInstance.wf_properties for both bus entries (range-check and XOR). 11 lemmas in 3 phases: - Phase A: bits_boolean (constraints 0-15 → boolean bit columns) - Phase B: binary_sum_lt_256, x_val_lt_256, y_val_lt_256 - Phase C: bit_xor_val, bit_xor_boolean, binary_sum_val_eq, nat_xor_binary_decomp, binary_xor_sum_correct The XOR correctness proof uses a compositional approach: lift Fin.val through arithmetic, convert per-bit XOR via a+b-2ab identity, then apply Nat.xor binary decomposition (proved over Fin 2 for decidability via native_decide). Co-Authored-By: Aristotle (Harmonic) <aristotle-harmonic@harmonic.fun> Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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Resolves INT-6543.
Overview
Update
BitwiseOperationLookupAir_8for the OpenVM v2.0.0-rc.1 layout, prove its bus well-formedness properties, and align its interaction wiring with the repo’sBitwiseBus.Code Changes
OpenvmFv/Airs/BitwiseOperationLookupAir_8.lean,OpenvmFv/Extraction/BitwiseOperationLookupAir_8.leanBitwiseOperationLookupAir_8x_bits_0..7,y_bits_0..7,mult_range,mult_xorBitwiseBus[x, y, 0, 0][x, y, xor, 1]OpenvmFv/Constraints/BitwiseOperationLookupAir_8.leanallHold/allHold_simplifiedinfrastructurex,y, andxorfrom the bit columnsx.val < 256andy.val < 256wf_properties_rangewf_properties_xorifflemmas connecting those theorems toInteraction.BitwiseBusEntryInstance.wf_propertiesBitwiseBusinstead of the stale bus6Hypotheses
The final well-formedness theorems assume:
all_constraints_hold air: the extracted/simplified constraints hold at every valid rowrow ≤ air.last_row: the theorem is stated only for valid trace rowsNo additional rotation-consistency or field-size hypothesis is needed for this proof.
Verification
lake build OpenvmFv.Constraints.BitwiseOperationLookupAir_8 OpenvmFv.Equivalence.BaseALU OpenvmFv.Equivalence.Mulh OpenvmFv.Equivalence.DivRem