Repositories list

• workshop-iu-kai

  Public
  SystemVerilog

  •0•0•0•0•Updated Nov 28, 2025Nov 28, 2025

• landing

  Public
  TypeScript

  •0•0•0•0•Updated Oct 27, 2025Oct 27, 2025

• platform-sum25-swp-vcd-team39

  Public archive
  JavaScript

  •

  MIT License

  •2•0•0•0•Updated Sep 19, 2025Sep 19, 2025

• project-schoolrv32i

  Public
  SystemVerilog

  •2•0•0•0•Updated Aug 4, 2025Aug 4, 2025

• project-Guitar-Processor-FPGA

  Public
  Jupyter Notebook

  •

  Apache License 2.0

  •1•0•0•0•Updated Jul 27, 2025Jul 27, 2025

• project-DoodleJumpFPGA

  Public
  SystemVerilog

  •

  MIT License

  •2•0•0•0•Updated Jul 26, 2025Jul 26, 2025

• project-fpga-uart-accelerator

  Public
  2•0•0•0•Updated Jul 24, 2025Jul 24, 2025

• club-website

  Public
  HTML

  •1•0•0•0•Updated Feb 19, 2025Feb 19, 2025

• project-Dino-Game-FPGA

  Public
  FPGA Project

  VHDL

  •3•0•0•0•Updated Dec 22, 2024Dec 22, 2024

• student-projects

  Public
  Repository with a list of FPGA student projects completed at Innopolis University during various courses

  0•0•0•0•Updated Oct 12, 2024Oct 12, 2024

• RiverRaidFPGA

  Public
  River Raid game on FPGA

  Verilog

  •3•0•0•0•Updated Oct 11, 2024Oct 11, 2024

• project-schoolRISCV

  Public archive
  CPU microarchitecture, step by step

  Makefile

  •

  Other

  •68•0•0•0•Updated Oct 10, 2024Oct 10, 2024

• project-F23_DCD_FPGA_Project

  Public archive
  Verilog

  •1•0•0•0•Updated Dec 19, 2023Dec 19, 2023

• project-DCD_MultiBankMemory

  Public archive
  SystemVerilog implementation of a multi-bank memory as part of "[F23] Digital Circuit Design" course

  SystemVerilog

  •

  MIT License

  •1•0•0•0•Updated Dec 19, 2023Dec 19, 2023

• project-SimpleCache

  Public archive
  Simple cache design implementation in verilog

  Verilog

  •

  MIT License

  •15•0•0•0•Updated Nov 20, 2023Nov 20, 2023

• project-Game2048_FPGA

  Public archive
  Verilog

  •1•0•0•0•Updated Jun 2, 2023Jun 2, 2023

• project-CA-Clicker-Game

  Public archive
  SystemVerilog

  •1•0•0•0•Updated Dec 12, 2022Dec 12, 2022

• project-StopWatch-FPGA

  Public
  Stopwatch implementation for FPGA

  Verilog

  •1•0•0•0•Updated Dec 10, 2022Dec 10, 2022

• project-Combinational_lock_code

  Public archive
  Verilog code for combinational lock on FPGA

  Verilog

  •

  GNU General Public License v3.0

  •3•0•0•0•Updated May 28, 2022May 28, 2022

• project-FPGA-Snake

  Public
  7-segment snake using a microcontroller

  SystemVerilog

  •1•0•0•0•Updated Nov 15, 2019Nov 15, 2019

• project-Real-time-edge-detection-on-FPGA

  Public archive
  Computer Architecture course's project Fall 2018, Innopolis University.

  Verilog

  •5•0•0•0•Updated Dec 6, 2018Dec 6, 2018

• project-SnakeGame_FPGA

  Public archive
  A snake game implemented in Verilog to run on FPGA

  Verilog

  •3•0•0•0•Updated Dec 5, 2018Dec 5, 2018

• project-Cube-Root

  Public archive
  CA project Fall 2018

  Verilog

  •1•0•0•0•Updated Nov 14, 2018Nov 14, 2018

• project-calculator

  Public archive
  CA project

  Verilog

  •1•0•0•0•Updated Nov 14, 2018Nov 14, 2018