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    306 repositories

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •20•103•19•8•Updated Jun 2, 2025Jun 2, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •67•263•17•23•Updated Jun 2, 2025Jun 2, 2025

    • pulp-c910

      Public
      SystemVerilog
      •
      Other
      •1•1•0•0•Updated Jun 2, 2025Jun 2, 2025

    • neureka

      Public
      2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
      SystemVerilog
      •
      Other
      •5•25•5•3•Updated Jun 2, 2025Jun 2, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •28•97•5•3•Updated Jun 2, 2025Jun 2, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •13•39•6•8•Updated Jun 2, 2025Jun 2, 2025

    • regression_tests

      Public
      C
      •18•8•3•1•Updated Jun 2, 2025Jun 2, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •37•48•7•4•Updated Jun 2, 2025Jun 2, 2025

    • picobello

      Public
      whatever it means
      SystemVerilog
      •
      Other
      •4•6•6•2•Updated Jun 2, 2025Jun 2, 2025

    • DeepQuant

      Public
      A Python library for true quantization of neural networks
      Python
      •
      Apache License 2.0
      •0•7•0•1•Updated May 31, 2025May 31, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •167•623•31•9•Updated May 31, 2025May 31, 2025

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •324•7•0•3•Updated May 30, 2025May 30, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •37•208•19•6•Updated May 30, 2025May 30, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •70•84•19•6•Updated May 30, 2025May 30, 2025

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •34•160•9•4•Updated May 30, 2025May 30, 2025

    • ManyRVData

      Public
      0•0•0•0•Updated May 30, 2025May 30, 2025

    • pulp-sdk

      Public
      C
      •
      Apache License 2.0
      •76•111•15•8•Updated May 29, 2025May 29, 2025

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •131•14•0•4•Updated May 28, 2025May 28, 2025

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •10•26•0•2•Updated May 28, 2025May 28, 2025

    • cluster_interconnect

      Public
      SystemVerilog
      •
      Other
      •15•13•1•3•Updated May 28, 2025May 28, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •16•62•1•3•Updated May 27, 2025May 27, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •22•108•1•7•Updated May 27, 2025May 27, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •49•294•3•5•Updated May 27, 2025May 27, 2025

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •4•14•1•5•Updated May 26, 2025May 26, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •294•1.3k•46•12•Updated May 26, 2025May 26, 2025

    • obi_peripherals

      Public
      Collection of peripheral IPs using the Open Bus Interface (OBI)
      Other
      •0•1•0•1•Updated May 24, 2025May 24, 2025

    • flex-v

      Public
      Core used inside the PULP cluster with mixed-precision MAC&LOAD (formerly RI5CY, now Flex-V)
      SystemVerilog
      •
      Other
      •1•1•0•0•Updated May 23, 2025May 23, 2025

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •149•429•76•5•Updated May 22, 2025May 22, 2025

    • llvm-project

      Public
      C++
      •14k•8•7•1•Updated May 22, 2025May 22, 2025

    • hwpe-ctrl

      Public
      IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •18•6•1•4•Updated May 21, 2025May 21, 2025