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    178 repositories

    • chipyard

      Public
      An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
      boomrocketrocket-chipchip-generatorchiselrtlperipheralssocout-of-ordersuperscalar
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •633•1.6k•177•20•Updated Oct 7, 2024Oct 7, 2024

    • saturn-vectors

      Public
      Chisel RISC-V Vector 1.0 Implementation
      cpuchiselvectorsrisc-vmicroarchitecturervv
      Assembly
      •
      BSD 3-Clause "New" or "Revised" License
      •3•43•2•1•Updated Oct 6, 2024Oct 6, 2024

    • riskybear-gym

      Public
      Python
      •
      Other
      •0•0•0•0•Updated Oct 6, 2024Oct 6, 2024

    • radiance

      Public
      Rocket Chip Generator
      SystemVerilog
      •
      Other
      •1.1k•1•0•0•Updated Oct 5, 2024Oct 5, 2024

    • Baremetal-NN

      Public
      A tool for converting PyTorch models into raw C codes that can be executed standalone in a baremetal runtime on RISC-V research chips.
      C
      •2•19•0•0•Updated Oct 4, 2024Oct 4, 2024

    • shuttle

      Public
      A Rocket-based RISC-V superscalar in-order core
      Scala
      •2•26•0•0•Updated Oct 3, 2024Oct 3, 2024

    • caliptra-aes-acc

      Public
      SystemVerilog
      •
      BSD 3-Clause "New" or "Revised" License
      •0•2•0•1•Updated Oct 3, 2024Oct 3, 2024

    • gemmini-rocc-tests

      Public
      Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
      C
      •
      Other
      •38•53•6•8•Updated Sep 30, 2024Sep 30, 2024

    • testchipip

      Public
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •59•80•15•4•Updated Sep 30, 2024Sep 30, 2024

    • blif-parser

      Public
      Rust
      •0•2•0•0•Updated Sep 30, 2024Sep 30, 2024

    • gemmini

      Public
      Berkeley's Spatial Array Generator
      asicacceleratordnn
      Scala
      •
      Other
      •160•785•77•12•Updated Sep 30, 2024Sep 30, 2024

    • RoSE

      Public
      A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •4•34•0•1•Updated Sep 27, 2024Sep 27, 2024

    • hammer

      Public
      Hammer: Highly Agile Masks Made Effortlessly from RTL
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •56•252•203•17•Updated Sep 26, 2024Sep 26, 2024

    • vexiiriscv-tile

      Public
      Chisel wrapper for the SpinalHDL VexiiRiscv CPU implementation, implementing Chipyard compatibility
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •0•0•0•0•Updated Sep 26, 2024Sep 26, 2024

    • riskybear-mechanical

      Public
      0•0•0•0•Updated Sep 26, 2024Sep 26, 2024

    • rerocc

      Public
      Scala
      •1•7•1•0•Updated Sep 26, 2024Sep 26, 2024

    • IsaacLab

      Public
      Unified framework for robot learning built on NVIDIA Isaac Sim
      Python
      •
      Other
      •794•0•0•0•Updated Sep 25, 2024Sep 25, 2024

    • Baremetal-IDE

      Public
      A submodule of Chipyard https://github.com/ucb-bar/chipyard
      HTML
      •5•7•5•1•Updated Sep 23, 2024Sep 23, 2024

    • spike-devices

      Public
      Collection of device models for spike
      C++
      •5•7•1•2•Updated Sep 16, 2024Sep 16, 2024

    • chipyard-cs152-sp24

      Public
      C
      •
      BSD 3-Clause "New" or "Revised" License
      •1•3•0•24•Updated Sep 13, 2024Sep 13, 2024

    • berkeley-hardfloat

      Public
      Scala
      •
      Other
      •87•288•17•3•Updated Sep 11, 2024Sep 11, 2024

    • Baremetal-BSP

      Public
      0•0•0•0•Updated Sep 9, 2024Sep 9, 2024

    • hammer-synopsys-plugins

      Public
      Hammer plugins for synopsys tools
      Python
      •
      Other
      •1•8•3•1•Updated Sep 9, 2024Sep 9, 2024

    • spyke

      Public
      Spyke, a RISC-V ISA Simulator in Python, for education purpose only, maybe
      0•2•0•0•Updated Sep 7, 2024Sep 7, 2024

    • riskybird

      Public
      C++
      •4•1•0•0•Updated Sep 6, 2024Sep 6, 2024

    • pyuartsi

      Public
      A standalone implementation of the Tethered Serial Interface (TSI) in Python.
      Python
      •0•5•0•0•Updated Sep 1, 2024Sep 1, 2024

    • constellation

      Public
      A Chisel RTL generator for network-on-chip interconnects
      hardwarechiselrtlsocnocinterconnectnetwork-on-chip
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •24•170•20•3•Updated Aug 23, 2024Aug 23, 2024

    • compress-acc

      Public
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •1•10•0•1•Updated Aug 22, 2024Aug 22, 2024

    • dosa

      Public
      DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators
      Python
      •
      BSD 2-Clause "Simplified" License
      •1•13•1•1•Updated Aug 22, 2024Aug 22, 2024

    • chiseltest

      Public archive
      The batteries-included testing and formal verification library for Chisel-based RTL designs.
      testingverificationchiselformal
      Scala
      •
      Other
      •73•220•47•16•Updated Aug 19, 2024Aug 19, 2024