Merge pull request #283 from os-fpga/bug/EDA-3304/post_synth_sim_fail

Bug/eda 3304/post synth sim fail
os-fpga · Oct 14, 2024 · 71e474b · 71e474b
2 parents f199f9c + 1a427da
commit 71e474b
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diff --git a/EDA-3304/clk_buf_primitive_inst/clk_buf_primitive_inst.ospr b/EDA-3304/clk_buf_primitive_inst/clk_buf_primitive_inst.ospr
@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--                                                   -->
+<!--Copyright (c) 2021-2022 The Open-Source FPGA Foundation.-->
+<Project Version="1.2.18">
+    <Configuration>
+        <Option Name="ID" Val="20241014101732707"/>
+        <Option Name="ActiveSimSet" Val="sim_1"/>
+        <Option Name="Project Type" Val="0"/>
+    </Configuration>
+    <CompilerConfig>
+        <Opt Name="LibPath" Val=""/>
+        <Opt Name="IncludePath" Val="./rtl"/>
+        <Opt Name="LibExt" Val=""/>
+        <Opt Name="Macro" Val=""/>
+    </CompilerConfig>
+    <SimulationConfig>
+        <Opt Name="LibPath" Val=""/>
+        <Opt Name="IncludePath" Val=""/>
+        <Opt Name="LibExt" Val=""/>
+        <Opt Name="Macro" Val=""/>
+    </SimulationConfig>
+    <IpConfig>
+        <Option Name="InstancePaths" Val=""/>
+        <Option Name="CatalogPaths" Val=""/>
+        <Option Name="InstanceCmds" Val=""/>
+    </IpConfig>
+    <FileSets>
+        <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="run_1/clk_buf_primitive_inst.srcs/constrs_1"/>
+        <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="run_1/clk_buf_primitive_inst.srcs/sim_1">
+            <File Path="$OSRCDIR/../sim/co_sim_tb/co_sim_clk_buf_primitive_inst.v"/>
+            <File Path="$OSRCDIR/../rtl/clk_buf_primitive_inst.v"/>
+            <Group Id="11" Name="unit_0" Files="$OSRCDIR/../sim/co_sim_tb/co_sim_clk_buf_primitive_inst.v" LibCommand="" LibName=""/>
+            <Group Id="11" Name="unit_1" Files="$OSRCDIR/../rtl/clk_buf_primitive_inst.v" LibCommand="" LibName=""/>
+            <Config>
+                <Option Name="TopModule" Val="co_sim_clk_buf_primitive_inst"/>
+                <Option Name="TopModuleLib" Val=""/>
+            </Config>
+        </FileSet>
+        <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="run_1/clk_buf_primitive_inst.srcs/sources_1">
+            <File Path="$OSRCDIR/../rtl/clk_buf_primitive_inst.v"/>
+            <Group Id="7" Name="unit_0" Files="$OSRCDIR/../rtl/clk_buf_primitive_inst.v" LibCommand="" LibName=""/>
+            <Config>
+                <Option Name="TopModule" Val="clk_buf_primitive_inst"/>
+                <Option Name="TopModuleLib" Val=""/>
+            </Config>
+        </FileSet>
+    </FileSets>
+    <Runs>
+        <Run Name="imple_1" Type="Implementation" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="synth_1"/>
+        <Run Name="synth_1" Type="Synthesis" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" SynthRun="">
+            <Option Name="Compilation Flow" Val="Classic Flow"/>
+            <Option Name="Device" Val="1VG28"/>
+            <Option Name="Family" Val="Virgo"/>
+            <Option Name="LanguageVersion" Val="SYSTEMVERILOG_2005"/>
+            <Option Name="Package" Val="F484A"/>
+            <Option Name="Series" Val="Virgo"/>
+            <Option Name="TargetLanguage" Val="VERILOG"/>
+        </Run>
+    </Runs>
+    <Tasks Version="0.0.0">
+        <Task ID="0" Status="0" Enable="1"/>
+        <Task ID="1" Status="2" Enable="1"/>
+        <Task ID="6" Status="0" Enable="1"/>
+        <Task ID="10" Status="0" Enable="1"/>
+        <Task ID="15" Status="0" Enable="1"/>
+        <Task ID="19" Status="0" Enable="1"/>
+        <Task ID="20" Status="0" Enable="1"/>
+        <Task ID="21" Status="0" Enable="0"/>
+        <Task ID="23" Status="2" Enable="1"/>
+        <Task ID="28" Status="0" Enable="1"/>
+        <Task ID="31" Status="3" Enable="1"/>
+        <Task ID="34" Status="0" Enable="1"/>
+        <Task ID="37" Status="0" Enable="1"/>
+    </Tasks>
+    <Compiler Version="0.0.0" CompilerState="3"/>
+</Project>
diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/analysis.rpt b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/analysis.rpt
@@ -0,0 +1,140 @@
+/*******************************************************************************
+Copyright (c) 2022-2024 Rapid Silicon
+This source code contains proprietary information belonging to Rapid Silicon
+(the "licensor") released under license and non-disclosure agreement to the
+recipient (the "licensee").
+
+The information shared and protected by the license and non-disclosure agreement
+includes but is not limited to the following:
+* operational algorithms of the product
+* logos, graphics, source code, and visual presentation of the product
+* confidential operational information of the licensor
+
+The recipient of this source code is NOT permitted to publicly disclose,
+re-use, archive beyond the period of the license agreement, transfer to a
+sub-licensee, or re-implement any portion of the content covered by the license
+and non-disclosure agreement without the prior written consent of the licensor.
+*********************************************************************************/
+
+Version  : 2024.10
+Build    : 1.2.18
+Hash     : 82370d4
+Date     : Oct 12 2024
+Type     : Engineering
+Log Time   : Mon Oct 14 05:17:32 2024 GMT
+/*******************************************************************************
+Copyright (c) 2022-2024 Rapid Silicon
+This source code contains proprietary information belonging to Rapid Silicon
+(the "licensor") released under license and non-disclosure agreement to the
+recipient (the "licensee").
+
+The information shared and protected by the license and non-disclosure agreement
+includes but is not limited to the following:
+* operational algorithms of the product
+* logos, graphics, source code, and visual presentation of the product
+* confidential operational information of the licensor
+
+The recipient of this source code is NOT permitted to publicly disclose,
+re-use, archive beyond the period of the license agreement, transfer to a
+sub-licensee, or re-implement any portion of the content covered by the license
+and non-disclosure agreement without the prior written consent of the licensor.
+*********************************************************************************/
+
+Version  : 2024.10
+Build    : 1.2.18
+Hash     : 82370d4
+Date     : Oct 12 2024
+Type     : Engineering
+Log Time   : Mon Oct 14 05:17:32 2024 GMT
+
+ /----------------------------------------------------------------------------\
+ |  yosys -- Yosys Open SYnthesis Suite                                       |
+ |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
+ |  Distributed under an ISC-like license, type "license" to see terms        |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3)
+
+-- Executing script file `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd' --
+
+1. Executing Verilog-2005 frontend: /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
+Parsing SystemVerilog input from `/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v' to AST representation.
+Generating RTLIL representation for module `\BOOT_CLOCK'.
+Generating RTLIL representation for module `\CARRY'.
+Generating RTLIL representation for module `\CLK_BUF'.
+Generating RTLIL representation for module `\DFFNRE'.
+Generating RTLIL representation for module `\DFFRE'.
+Generating RTLIL representation for module `\DLY_SEL_DCODER'.
+Generating RTLIL representation for module `\DLY_SEL_DECODER'.
+Generating RTLIL representation for module `\DLY_VALUE_MUX'.
+Generating RTLIL representation for module `\DSP19X2'.
+Generating RTLIL representation for module `\DSP38'.
+Generating RTLIL representation for module `\FCLK_BUF'.
+Generating RTLIL representation for module `\FIFO18KX2'.
+Generating RTLIL representation for module `\FIFO36K'.
+Generating RTLIL representation for module `\I_BUF_DS'.
+Generating RTLIL representation for module `\I_BUF'.
+Generating RTLIL representation for module `\I_DDR'.
+Generating RTLIL representation for module `\I_DELAY'.
+Generating RTLIL representation for module `\I_FAB'.
+Generating RTLIL representation for module `\I_SERDES'.
+Generating RTLIL representation for module `\LATCHNR'.
+Generating RTLIL representation for module `\LATCHNS'.
+Generating RTLIL representation for module `\LATCHN'.
+Generating RTLIL representation for module `\LATCHR'.
+Generating RTLIL representation for module `\LATCHS'.
+Generating RTLIL representation for module `\LATCH'.
+Generating RTLIL representation for module `\LUT1'.
+Generating RTLIL representation for module `\LUT2'.
+Generating RTLIL representation for module `\LUT3'.
+Generating RTLIL representation for module `\LUT4'.
+Generating RTLIL representation for module `\LUT5'.
+Generating RTLIL representation for module `\LUT6'.
+Generating RTLIL representation for module `\MIPI_RX'.
+Generating RTLIL representation for module `\MIPI_TX'.
+Generating RTLIL representation for module `\O_BUF_DS'.
+Generating RTLIL representation for module `\O_BUFT_DS'.
+Generating RTLIL representation for module `\O_BUFT'.
+Generating RTLIL representation for module `\O_BUF'.
+Generating RTLIL representation for module `\O_DDR'.
+Generating RTLIL representation for module `\O_DELAY'.
+Generating RTLIL representation for module `\O_FAB'.
+Generating RTLIL representation for module `\O_SERDES_CLK'.
+Generating RTLIL representation for module `\O_SERDES'.
+Generating RTLIL representation for module `\PLL'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_M'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AHB_S'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M0'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_AXI_M1'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_DMA'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_IRQ'.
+Generating RTLIL representation for module `\SOC_FPGA_INTF_JTAG'.
+Generating RTLIL representation for module `\SOC_FPGA_TEMPERATURE'.
+Generating RTLIL representation for module `\TDP_RAM18KX2'.
+Generating RTLIL representation for module `\TDP_RAM36K'.
+Successfully finished Verilog frontend.
+
+2. Executing Verilog-2005 frontend: /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v
+Parsing Verilog input from `/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v' to AST representation.
+Generating RTLIL representation for module `\clk_buf_primitive_inst'.
+Successfully finished Verilog frontend.
+
+-- Running command `hierarchy -top clk_buf_primitive_inst' --
+
+3. Executing HIERARCHY pass (managing design hierarchy).
+
+3.1. Analyzing design hierarchy..
+Top module:  \clk_buf_primitive_inst
+
+3.2. Analyzing design hierarchy..
+Top module:  \clk_buf_primitive_inst
+Removed 0 unused modules.
+
+Dumping file hier_info.json ...
+ Process module "CLK_BUF"
+ Process module "I_BUF"
+Dumping file port_info.json ...
+
+End of script. Logfile hash: 835a24a3cc, CPU: user 0.02s system 0.01s, MEM: 15.87 MB peak
+Yosys 0.44 (git sha1 7a4a3768c, g++ 11.2.1 -fPIC -O3)
+Time spent: 94% 4x read_verilog (0 sec), 4% 1x analyze (0 sec), ...
diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/clk_buf_primitive_inst_analyzer.cmd
@@ -0,0 +1,5 @@
+read_verilog -sv /nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v
+verilog_defines 
+read_verilog  -I../../../.././rtl -I../../../../ -I/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl  /nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v 
+
+analyze -top clk_buf_primitive_inst
diff --git a/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/hier_info.json b/EDA-3304/clk_buf_primitive_inst/run_1/synth_1_1/analysis/hier_info.json
@@ -0,0 +1,158 @@
+{
+  "fileIDs": {
+      "1": "/nfs_eda_sw/softwares/Raptor/instl_dir/10_12_2024_09_15_01/share/raptor/sim_models/rapidsilicon/genesis3/FPGA_PRIMITIVES_MODELS/blackbox_models/cell_sim_blackbox.v",
+      "2": "/nfs_scratch/scratch/CompilerValidation/zaheer_ahmad/os_fpga2/Validation/RTL_testcases/RS_FPGA_PRIMITIVES_new/clk_buf_primitive_inst/./rtl/clk_buf_primitive_inst.v"
+  },
+  "hierTree": [
+      {
+          "file": "2",
+          "internalSignals": [
+              {
+                  "name": "wire1",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              },
+              {
+                  "name": "wire2",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              },
+              {
+                  "name": "wire_out_clk",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              }
+          ],
+          "language": "SystemVerilog",
+          "line": 1,
+          "moduleInsts": [
+              {
+                   "file": "2",
+                   "instName": "clk_buf_inst",
+                   "line": 21,
+                   "module":  "CLK_BUF",
+                   "parameters": []
+              },
+              {
+                   "file": "2",
+                   "instName": "i_buf_inst",
+                   "line": 10,
+                   "module":  "I_BUF",
+                   "parameters": []
+              }
+          ],
+          "ports": [
+              {
+                  "direction": "Input",
+                  "name": "clock_input",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              },
+              {
+                  "direction": "Input",
+                  "name": "ibuf_enable",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              },
+              {
+                  "direction": "Output",
+                  "name": "clock_output",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              }
+          ],
+          "topModule": "clk_buf_primitive_inst"
+      }
+  ],
+  "modules": {
+      "CLK_BUF": {
+          "file": "1",
+          "language": "SystemVerilog",
+          "line": 41,
+          "module": "CLK_BUF",
+          "ports": [
+              {
+                  "direction": "Input",
+                  "name": "I",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              },
+              {
+                  "direction": "Output",
+                  "name": "O",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              }
+          ]
+      },
+      "I_BUF": {
+          "file": "1",
+          "language": "SystemVerilog",
+          "line": 406,
+          "module": "I_BUF",
+          "parameters": [
+              {
+                  "name": "IOSTANDARD",
+                  "value": 0 
+              },
+              {
+                  "name": "WEAK_KEEPER",
+                  "value": 0 
+              }
+          ],
+          "ports": [
+              {
+                  "direction": "Input",
+                  "name": "I",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              },
+              {
+                  "direction": "Input",
+                  "name": "EN",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              },
+              {
+                  "direction": "Output",
+                  "name": "O",
+                  "range": {
+                      "lsb": 0,
+                      "msb": 0
+                  },
+                  "type": "LOGIC"
+              }
+          ]
+      }
+  }
+}