Add new synth option to readme and bump patch version (#2101)

* Add new synth option * Update README.md * Update CMakeLists.txt
os-fpga · Nov 25, 2024 · 4ebe053 · 4ebe053
1 parent b858f85
commit 4ebe053
Show file tree

Hide file tree

Showing 2 changed files with 27 additions and 23 deletions.
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -290,7 +290,7 @@ add_subdirectory(IP_Catalog)
 # Raptor version
 set(VERSION_MAJOR 1)
 set(VERSION_MINOR 2)
-set(VERSION_PATCH 31)
+set(VERSION_PATCH 32)
 
 execute_process(COMMAND git config --global --add safe.directory ${CMAKE_CURRENT_SOURCE_DIR}
   COMMAND git rev-parse --short HEAD

diff --git a/README.md b/README.md
@@ -118,30 +118,35 @@ Tcl commands (Available in GUI or Batch console or Batch script):
 --- Synthesis ---
 -----------------
    synth_options <option list>:
-     -effort <level>          : Optimization effort level (high, medium, low)
-       high                   : Most compute, generally impacting runtime (default)
-       medium                 : Balanced compute
-       low                    : least compute, least runtime
-     -fsm_encoding <encoding> : FSM encoding (binary, onehot)
-       binary                 : Compact encoding - using minimum of registers to cover the N states
-       onehot                 : One hot encoding - using N registers for N states (default)
-     -carry <mode>            : Carry logic inference mode (all, auto, none)
-       all                    : Infer as much as possible
-       auto                   : Infer carries based on internal heuristics (default)
-       none                   : Do not infer carries
-     -clke_strategy <strategy>: Clock enable extraction strategy for FFs (early, late)
-       early                  : Perform early extraction (default)
-       late                   : Perform late extraction
-     -fast                    : Perform the fastest synthesis. QoR can be impacted.
-     -no_flatten              : Do not flatten design.
-     -no_simplify             : Do not run special simplification algorithms in synthesis.
-     -no_tribuf               : Do not preserve I/O tristate buffers
-     -no_adder                : Do not infer adders
-     -inferred_io             : Automatic I/O inference (Default false for eFPGA)
-     -no_inferred_io          : No automatic I/O inference (Default true for FPGA)     
+     -effort <level>            : Optimization effort level (high, medium, low)
+       high                     : Most compute, generally impacting runtime (default)
+       medium                   : Balanced compute
+       low                      : least compute, least runtime
+     -fsm_encoding <encoding>   : FSM encoding (binary, onehot)
+       binary                   : Compact encoding - using minimum of registers to cover the N states
+       onehot                   : One hot encoding - using N registers for N states (default)
+     -carry <mode>              : Carry logic inference mode (all, auto, none)
+       all                      : Infer as much as possible
+       auto                     : Infer carries based on internal heuristics (default)
+       none                     : Do not infer carries
+     -clke_strategy <strategy>  : Clock enable extraction strategy for FFs (early, late)
+       early                    : Perform early extraction (default)
+       late                     : Perform late extraction
+     -fast                      : Perform the fastest synthesis. QoR can be impacted
+     -no_flatten                : Do not flatten design
+     -no_simplify               : Do not run special simplification algorithms in synthesis
+     -no_tribuf                 : Do not preserve I/O tristates
+     -no_adder                  : Do not infer adders
+     -inferred_io               : Automatic I/O inference (Default false for eFPGA)
+     -no_inferred_io            : No automatic I/O inference (Default true for FPGA)
+     -read_init_registers <int> : Force initialization to uninitialized registers (0, 1, 2)
+       0                        : Initialize register by '0' (default)
+       1                        : Initialize register by '1'
+       2                        : Leave register unintialized
    set_limits <type> <int>    : Sets a user limit on object of type (dsp, bram), specify 0 to disable block inferrence
        dsp                    : Maximum number of usable DSPs
        bram                   : Maximum number of usable BRAMs
+       carry_length           : Maximum carry length
    analyze ?clean?            : Analyzes the RTL design, generates top-level, pin and hierarchy information
      clean                    : Deletes files generated from this task
    synthesize <optimization>  ?clean? : RTL Synthesis, optional opt. (area, delay, mixed)
@@ -150,7 +155,6 @@ Tcl commands (Available in GUI or Batch console or Batch script):
        delay                  : Optimize for performance
        mixed                  : Optimize for area and performance (default)
      clean                    : Deletes files generated from this task
-
 ---------------
 --- Packing ---
 ---------------