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Merge pull request #432 from os-fpga/cic_decimator
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updated the rtl of cic_decimator and added setup_lec_sim
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NadeemYaseen authored Oct 31, 2024
2 parents 0617f1b + 4b8d44c commit bc8b4ce
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Showing 13 changed files with 16 additions and 8 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ start=`date +%s`
design="cic_d"
ip_name="" #design_level
#select tool (verilator, vcs, ghdl, iverilog)
tool_name="iverilog"
tool_name="verilator"

#simulation stages
post_synth_sim=false
Expand Down Expand Up @@ -182,9 +182,14 @@ parse_cga exit 1; }
[ -z "$ip_name" ] && echo "" || echo "add_design_file ./rapidsilicon/ip/$ip_name/v1_0/$design/src/$design.v">>raptor_tcl.tcl

[ -z "$ip_name" ] && echo "add_include_path ./rtl">>raptor_tcl.tcl || echo ""
[ -z "$ip_name" ] && echo "add_library_path ./rtl">>raptor_tcl.tcl || echo ""
[ -z "$ip_name" ] && echo "add_library_ext .v .sv">>raptor_tcl.tcl || echo ""
[ -z "$ip_name" ] && echo "add_design_file ./rtl/$design.sv">>raptor_tcl.tcl || echo ""
# [ -z "$ip_name" ] && echo "add_library_path ./rtl">>raptor_tcl.tcl || echo ""
# [ -z "$ip_name" ] && echo "add_library_ext .v .sv">>raptor_tcl.tcl || echo ""
[ -z "$ip_name" ] && echo "add_design_file ./rtl/cic_package.sv">>raptor_tcl.tcl || echo ""
[ -z "$ip_name" ] && echo "add_design_file ./rtl/comb.sv">>raptor_tcl.tcl || echo ""
[ -z "$ip_name" ] && echo "add_design_file ./rtl/downsampler.sv">>raptor_tcl.tcl || echo ""
[ -z "$ip_name" ] && echo "add_design_file ./rtl/integrator.sv">>raptor_tcl.tcl || echo ""
[ -z "$ip_name" ] && echo "add_design_file ./rtl/cic_i.sv">>raptor_tcl.tcl || echo ""
[ -z "$ip_name" ] && echo "add_design_file ./rtl/cic_d.sv">>raptor_tcl.tcl || echo ""
##vary design to design

echo "set_top_module $design">>raptor_tcl.tcl
Expand All @@ -205,6 +210,8 @@ parse_cga exit 1; }
[ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl
[ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl
[ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl
echo "setup_lec_sim">>raptor_tcl.tcl
[ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl
if [ "$post_synth_sim" == true ]; then
echo "# Open the input file in read mode">>raptor_tcl.tcl
echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl
Expand Down Expand Up @@ -258,6 +265,7 @@ parse_cga exit 1; }
else
echo ""
fi
[ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl
echo "sta">>raptor_tcl.tcl
echo "power">>raptor_tcl.tcl
echo "bitstream $bitstream">>raptor_tcl.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ function longint nchoosek;
longint tmp;
longint i;
begin
tmp = 1.0;
tmp = 1;
for (i=1;i<=(n-k);i++)
tmp = tmp*(k+i)/i;
nchoosek = tmp;
Expand Down Expand Up @@ -35,7 +35,7 @@ function longint h;
begin
c_stop = k/(R*M);
if ((j>=1)&&(j<=N)) begin
tmp=0.0;
tmp=0;
for (i=0;i<=c_stop;i++) begin
if (i%2)
tmp = tmp - nchoosek(N,i)*nchoosek(N-j+k-R*M*i,k-R*M*i);
Expand All @@ -61,7 +61,7 @@ function longint F;
longint tmp;
longint i;
begin
tmp = 0.0;
tmp = 0;
if (j<=M)
c_stop=(((R*G-1)*M)+j-1);
else
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ module downsampler
input clk,
input reset_n,
input [dw-1:0] data_in,
output reg [dw-1:0] data_out,
output reg signed [dw-1:0] data_out,
output reg dv
);
/*********************************************************************************************/
Expand Down

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