Merge pull request #438 from os-fpga/task/EDA-3187/add_setup_lec_sim

updated rtl and added setup_lec_sim for divider

RTL_testcases/RTL_Benchmarks_Gap_Analysis/divider/raptor_run.sh

@@ -262,6 +262,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/divider/rtl/div_su.v

@@ -75,16 +75,17 @@ module div_su(clk, ena, z, d, q, s, div0, ovf);
 	output div0;
 	output ovf;
 
-	reg [d_width:0] q, s;
-	reg div0;
-	reg ovf;
+	reg [d_width:0] q = 0;
+	reg [d_width:0] s = 0;
+	reg div0 = 0;
+	reg ovf = 0;
 
 	//
 	// variables
 	//
-	reg [z_width -1:0] iz;
-	reg [d_width -1:0] id;
-	reg [d_width +1:0] spipe;
+	reg [z_width -1:0] iz = 0;
+	reg [d_width -1:0] id = 1;
+	reg [d_width +1:0] spipe = 0;
 
 	wire [d_width -1:0] iq, is;
 	wire                idiv0, iovf;
@@ -132,7 +133,7 @@ module div_su(clk, ena, z, d, q, s, div0, ovf);
 
 	// correct divider results if 'd' was negative
 	always @(posedge clk)
-	  if(ena)
+	  if(ena) begin
 	    if(spipe[d_width+1])
 	    begin
 	        q <= #1 (~iq) + 1'h1;
@@ -143,6 +144,7 @@ module div_su(clk, ena, z, d, q, s, div0, ovf);
 	        q <= #1 {1'b0, iq};
 	        s <= #1 {1'b0, is};
 	    end
+	end
 
 	// delay flags same as results
 	always @(posedge clk)

RTL_testcases/RTL_Benchmarks_Gap_Analysis/divider/rtl/div_uu.v

@@ -76,10 +76,10 @@ module div_uu(clk, ena, z, d, q, s, div0, ovf);
 	output [d_width -1:0] s; // remainder
 	output div0;
 	output ovf;
-	reg [d_width-1:0] q;
-	reg [d_width-1:0] s;
-	reg div0;
-	reg ovf;
+	reg [d_width-1:0] q = 0;
+	reg [d_width-1:0] s = 0;
+	reg div0 = 0;
+	reg ovf = 0;
 
 	//	
 	// functions
@@ -124,7 +124,30 @@ module div_uu(clk, ena, z, d, q, s, div0, ovf);
 	reg [z_width:0] s_pipe  [d_width:0];
 	reg [z_width:0] d_pipe  [d_width:0];
 
-	reg [d_width:0] div0_pipe, ovf_pipe;
+	reg [d_width:0] div0_pipe = 1;
+	reg [d_width:0] ovf_pipe = 0;
+
+	// Initialize q_pipe with zeros
+	integer i;
+	initial begin
+	    for (i = 0; i < d_width; i = i + 1) begin
+	        q_pipe[i] = {d_width{1'b0}}; // Set each element to a zero of d_width bits
+	    end
+	end
+
+	// integer i;
+	initial begin
+	    for (i = 0; i <= d_width; i = i + 1) begin
+	        s_pipe[i] = {d_width{1'b0}}; // Set each element to a zero of d_width bits
+	    end
+	end
+
+	// integer i;
+	initial begin
+	    for (i = 0; i <= d_width; i = i + 1) begin
+	        d_pipe[i] = {d_width{1'b0}}; // Set each element to a zero of d_width bits
+	    end
+	end
 	//
 	// perform parameter checks
 	//
@@ -140,7 +163,7 @@ module div_uu(clk, ena, z, d, q, s, div0, ovf);
 
 	// generate divisor (d) pipe
 	always @(d)
-	  d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
+	  d_pipe[0] <= {(z_width-d_width){1'b0}};
 
 	always @(posedge clk)
 	  if(ena)
@@ -149,7 +172,7 @@ module div_uu(clk, ena, z, d, q, s, div0, ovf);
 
 	// generate internal remainder pipe
 	always @(z)
-	  s_pipe[0] <= z;
+	  s_pipe[0] <= z[0];
 
 	always @(posedge clk)
 	  if(ena)
@@ -170,16 +193,24 @@ module div_uu(clk, ena, z, d, q, s, div0, ovf);
 	always @(z or d)
 	begin
 	  ovf_pipe[0]  <= !(z[z_width-1:d_width] < d);
-	  div0_pipe[0] <= ~|d;
+	  div0_pipe[0] <= ~|d[7];
 	end
 
 	always @(posedge clk)
-	  if(ena)
+	  if(ena) begin
 	    for(n3=1; n3 <= d_width; n3=n3+1)
 	    begin
 	        ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
 	        div0_pipe[n3] <= #1 div0_pipe[n3-1];
 	    end
+	  end
+	  else begin
+	    for(n3=1; n3 <= d_width; n3=n3+1)
+	    begin
+	        ovf_pipe[n3] <= 'b0;
+	        div0_pipe[n3] <= 'b0;
+	    end
+	  end
 
 	// assign outputs
 	always @(posedge clk)