Merge pull request #442 from os-fpga/task/EDA-3187/add_setup_lec_sim

added setup_lec_sim for 3 designs
os-fpga · Nov 6, 2024 · f1c44cd · f1c44cd
2 parents 7f0b16d + a29e1e3
commit f1c44cd
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Showing 3 changed files with 11 additions and 1 deletion.
diff --git a/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP19x2_primitive_inst/raptor_run.sh b/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP19x2_primitive_inst/raptor_run.sh
@@ -258,6 +258,10 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "clear_simulation_files">>raptor_tcl.tcl 
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

diff --git a/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP38_primitive_inst/raptor_run.sh b/RTL_testcases/RS_FPGA_PRIMITIVES_new/DSP38_primitive_inst/raptor_run.sh
@@ -258,6 +258,10 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "clear_simulation_files">>raptor_tcl.tcl 
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

diff --git a/RTL_testcases/test_vpr_xml_for_enhanced_DSP_features/dsp_xml_test/raptor_run.sh b/RTL_testcases/test_vpr_xml_for_enhanced_DSP_features/dsp_xml_test/raptor_run.sh
@@ -7,7 +7,7 @@ start=`date +%s`
 design="dsp_xml_test"
 ip_name="" #design_level
 #select tool (verilator, vcs, ghdl, iverilog)
-tool_name="iverilog" 
+tool_name="verilator" 
 
 #simulation stages
 post_synth_sim=false 
@@ -205,6 +205,8 @@ parse_cga exit 1; }
     [ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl
     [ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl
     [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl  
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
     if [ "$post_synth_sim" == true ]; then 
         echo "# Open the input file in read mode">>raptor_tcl.tcl 
         echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl