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pavanholla / WISC-SP13 Public

forked from ngwilliams/WISC-SP13

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WISC-SP13

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WISC-SP13

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The WISC-SP13 processor was created for cs552 Introduction to Computer Architecture. It is a five stage pipelined processor based off of a MIPS ISA. Features include a cache, branch prediction, and stalling memory.

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