GitHub - pavanholla/WISC-SP13

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
ALUControl.v		ALUControl.v
Alu.v		Alu.v
BTR.v		BTR.v
BranchForwardingUnit.v		BranchForwardingUnit.v
CLA4Bit.v		CLA4Bit.v
CLA_16bit.v		CLA_16bit.v
DataForwardingUnit.v		DataForwardingUnit.v
HazardDetectionUnit.v		HazardDetectionUnit.v
I_Decode.v		I_Decode.v
I_Execute.v		I_Execute.v
I_Fetch_withICache.v		I_Fetch_withICache.v
I_Memory.v		I_Memory.v
I_WriteBack.v		I_WriteBack.v
LeftShift16_16.v		LeftShift16_16.v
README.txt		README.txt
ROR.v		ROR.v
RegIdentifier.v		RegIdentifier.v
RippleCarryAdder.v		RippleCarryAdder.v
RippleCarryAdder16.v		RippleCarryAdder16.v
ShiftLeftOne11_12.v		ShiftLeftOne11_12.v
ShiftLeftOne16_16.v		ShiftLeftOne16_16.v
SignExtend11_16.v		SignExtend11_16.v
SignExtend8_16.v		SignExtend8_16.v
adder.v		adder.v
cache.v		cache.v
cache_2way.v		cache_2way.v
clkrst.v		clkrst.v
control.v		control.v
decoder3_8.v		decoder3_8.v
dff.v		dff.v
dffe.v		dffe.v
final_memory.syn.v		final_memory.syn.v
four_bank_mem.v		four_bank_mem.v
left_rotate.v		left_rotate.v
left_shift.v		left_shift.v
mem_system.v		mem_system.v
mem_system_ctrl.v		mem_system_ctrl.v
memc.syn.v		memc.syn.v
memc.v		memc.v
memv.syn.v		memv.syn.v
mux2_1.v		mux2_1.v
mux4_1.v		mux4_1.v
mux8_1.v		mux8_1.v
nand2.v		nand2.v
nor16.v		nor16.v
nor2.v		nor2.v
not1.v		not1.v
proc.v		proc.v
proc_hier.v		proc_hier.v
reg_16bit.v		reg_16bit.v
rf.v		rf.v
rf_bypass.v		rf_bypass.v
right_logical.v		right_logical.v
shifter.v		shifter.v
statelogic.v		statelogic.v
statereg.v		statereg.v
xor2.v		xor2.v

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The WISC-SP13 processor was created for cs552 Introduction to Computer Architecture. It is a five stage pipelined processor based off of a MIPS ISA. Features include a cache, branch prediction, and stalling memory.