arty_def_val.txt

BOARD_PART:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
COMPXLIB.ACTIVEHDL_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/compile_simlib/activehdl)==CURRENT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/compile_simlib/activehdl)
COMPXLIB.FUNCSIM:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
COMPXLIB.MODELSIM_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/compile_simlib/modelsim)==CURRENT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/compile_simlib/modelsim)
COMPXLIB.OVERWRITE_LIBS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
COMPXLIB.QUESTA_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/compile_simlib/questa)==CURRENT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/compile_simlib/questa)
COMPXLIB.RIVIERA_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/compile_simlib/riviera)==CURRENT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/compile_simlib/riviera)
COMPXLIB.TIMESIM:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
COMPXLIB.VCS_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/compile_simlib/vcs)==CURRENT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/compile_simlib/vcs)
COMPXLIB.XSIM_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
CORECONTAINER.ENABLE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
CUSTOMIZED_DEFAULT_IP_LOCATION:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
DEFAULT_LIB:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xil_defaultlib)
ENABLE_OPTIONAL_RUNS_STA:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
ENABLE_RESOURCE_ESTIMATION:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (0)
ENABLE_VHDL_2008:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
FEATURE_SET:(string) DEFAULT_VALUE ()==CURRENT_VALUE (FeatureSet_Classic)
GENERATE_IP_UPGRADE_LOG:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
IP.USER_FILES_DIR:(string) DEFAULT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.ip_user_files)==CURRENT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.ip_user_files)
IP_CACHE_PERMISSIONS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE (read write)
IP_INTERFACE_INFERENCE_PRIORITY:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
IP_OUTPUT_REPO:(string) DEFAULT_VALUE ()==CURRENT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.cache/ip)
IS_READONLY:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
LEGACY_IP_REPO_PATHS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
LOCAL_IP_REPO_LEAF_DIR_NAME:(enum) DEFAULT_VALUE (ip_repo)==CURRENT_VALUE (ip_repo)
MEM.ENABLE_MEMORY_MAP_GENERATION:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
PART:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xc7a35ticsg324-1L)
PLATFORM.DEFAULT_OUTPUT_TYPE:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (undefined)
PLATFORM.DESIGN_INTENT.DATACENTER:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (undefined)
PLATFORM.DESIGN_INTENT.EMBEDDED:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (undefined)
PLATFORM.DESIGN_INTENT.EXTERNAL_HOST:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (undefined)
PLATFORM.DESIGN_INTENT.SERVER_MANAGED:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (undefined)
PLATFORM.ROM.DEBUG_TYPE:(int) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PLATFORM.ROM.PROM_TYPE:(int) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PLATFORM.SLRCONSTRAINTMODE:(int) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PREFERRED_SIM_MODEL:(string) DEFAULT_VALUE (rtl)==CURRENT_VALUE (rtl)
PROJECT_TYPE:(enum) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
PR_FLOW:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
REVISED_DIRECTORY_STRUCTURE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
SIM.CENTRAL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.ip_user_files)
SIM.IP.AUTO_EXPORT_SCRIPTS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
SIM.IPSTATIC.SOURCE_DIR:(string) DEFAULT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.ip_user_files/ipstatic)==CURRENT_VALUE (/home/pawel/hippomenes/hippomenes/fpga/arty/arty.ip_user_files/ipstatic)
SIM.USE_IP_COMPILED_LIBS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
SIMULATOR.ACTIVEHDL_GCC_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.ACTIVEHDL_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.MODELSIM_GCC_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.MODELSIM_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.QUESTA_GCC_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.QUESTA_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.RIVIERA_GCC_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.RIVIERA_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.VCS_GCC_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.VCS_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.XCELIUM_GCC_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.XCELIUM_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR_LANGUAGE:(enum) DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Mixed)
SIM_COMPILE_STATE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
SOURCE_MGMT_MODE:(enum) DEFAULT_VALUE (All)==CURRENT_VALUE (All)
TARGET_LANGUAGE:(enum) DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog)
TARGET_SIMULATOR:(string) DEFAULT_VALUE (XSim)==CURRENT_VALUE (XSim)
TOOL_FLOW:(enum) DEFAULT_VALUE (Vivado)==CURRENT_VALUE (Vivado)
WEBTALK.ACTIVEHDL_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (4)
WEBTALK.MODELSIM_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (4)
WEBTALK.QUESTA_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (4)
WEBTALK.RIVIERA_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (4)
WEBTALK.VCS_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (4)
WEBTALK.XSIM_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (4)
WEBTALK.XSIM_LAUNCH_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (98)
XPM_LIBRARIES:(string*) DEFAULT_VALUE ()==CURRENT_VALUE (XPM_CDC)
XSIM.ARRAY_DISPLAY_LIMIT:(string) DEFAULT_VALUE (1024)==CURRENT_VALUE (1024)
XSIM.RADIX:(enum) DEFAULT_VALUE (hex)==CURRENT_VALUE (hex)
XSIM.TIME_UNIT:(enum) DEFAULT_VALUE (ns)==CURRENT_VALUE (ns)
XSIM.TRACE_LIMIT:(string) DEFAULT_VALUE (65536)==CURRENT_VALUE (65536)
decoder_pkg.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
decoder_pkg.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
decoder_pkg.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
decoder_pkg.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
decoder_pkg.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
decoder_pkg.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
decoder_pkg.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
decoder_pkg.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
decoder_pkg.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
alu.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
alu.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
alu.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
alu.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
alu.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu_a_mux.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
alu_a_mux.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu_a_mux.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
alu_a_mux.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
alu_a_mux.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
alu_a_mux.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
alu_a_mux.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu_a_mux.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu_a_mux.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu_b_mux.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
alu_b_mux.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu_b_mux.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
alu_b_mux.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
alu_b_mux.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
alu_b_mux.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
alu_b_mux.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu_b_mux.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
alu_b_mux.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
config_pkg.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
config_pkg.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
config_pkg.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
config_pkg.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
config_pkg.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
config_pkg.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
config_pkg.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
config_pkg.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
config_pkg.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
arty_pkg.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
arty_pkg.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
arty_pkg.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
arty_pkg.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
arty_pkg.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
arty_pkg.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
arty_pkg.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
arty_pkg.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
arty_pkg.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
branch_logic.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
branch_logic.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
branch_logic.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
branch_logic.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
branch_logic.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
branch_logic.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
branch_logic.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
branch_logic.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
branch_logic.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
csr.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
csr.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
csr.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
csr.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
csr.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
csr.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
csr.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
csr.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
csr.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mem_pkg.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
mem_pkg.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mem_pkg.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
mem_pkg.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
mem_pkg.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
mem_pkg.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
mem_pkg.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mem_pkg.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mem_pkg.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
d_mem_spram.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
d_mem_spram.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
d_mem_spram.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
d_mem_spram.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
d_mem_spram.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
d_mem_spram.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
d_mem_spram.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
d_mem_spram.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
d_mem_spram.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
decoder.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
decoder.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
decoder.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
decoder.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
decoder.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
decoder.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
decoder.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
decoder.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
decoder.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fifo.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
fifo.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fifo.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fifo.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fifo.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fifo.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
fifo.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fifo.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fifo.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mul.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
mul.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mul.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
mul.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
mul.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
mul.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
mul.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mul.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
mul.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
n_clic.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
n_clic.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
n_clic.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
n_clic.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
n_clic.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
n_clic.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
n_clic.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
n_clic.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
n_clic.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_adder.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
pc_adder.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_adder.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
pc_adder.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
pc_adder.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
pc_adder.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
pc_adder.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_adder.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_adder.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_branch_mux.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
pc_branch_mux.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_branch_mux.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
pc_branch_mux.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
pc_branch_mux.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
pc_branch_mux.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
pc_branch_mux.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_branch_mux.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_branch_mux.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_interrupt_mux.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
pc_interrupt_mux.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_interrupt_mux.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
pc_interrupt_mux.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
pc_interrupt_mux.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
pc_interrupt_mux.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
pc_interrupt_mux.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_interrupt_mux.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
pc_interrupt_mux.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
reg_n.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
reg_n.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
reg_n.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
reg_n.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
reg_n.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
reg_n.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
reg_n.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
reg_n.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
reg_n.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
register_file.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
register_file.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
register_file.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
register_file.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
register_file.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
register_file.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
register_file.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
register_file.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
register_file.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
rf_stack.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
rf_stack.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
rf_stack.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
rf_stack.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
rf_stack.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
rf_stack.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
rf_stack.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
rf_stack.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
rf_stack.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
spram.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
spram.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
spram.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
spram.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
spram.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
spram.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
spram.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
spram.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
spram.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
spram_block.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
spram_block.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
spram_block.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
spram_block.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
spram_block.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
spram_block.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
spram_block.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
spram_block.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
spram_block.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
stack.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
stack.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
stack.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
stack.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
stack.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
stack.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
stack.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
stack.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
stack.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
timer.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
timer.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
timer.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
timer.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
timer.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
timer.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
timer.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
timer.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
timer.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
top_arty.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
top_arty.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
top_arty.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
top_arty.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
top_arty.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
top_arty.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
top_arty.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
top_arty.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
top_arty.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
uart.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
uart.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
uart.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
uart.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
uart.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
uart.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
uart.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
uart.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
uart.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
vcsr.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
vcsr.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
vcsr.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
vcsr.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
vcsr.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
vcsr.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
vcsr.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
vcsr.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
vcsr.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wb_mem_mux.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
wb_mem_mux.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wb_mem_mux.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
wb_mem_mux.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
wb_mem_mux.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
wb_mem_mux.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
wb_mem_mux.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wb_mem_mux.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wb_mem_mux.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wb_mux.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
wb_mux.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wb_mux.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
wb_mux.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
wb_mux.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
wb_mux.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
wb_mux.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wb_mux.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wb_mux.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wt_ctl.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
wt_ctl.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wt_ctl.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
wt_ctl.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
wt_ctl.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
wt_ctl.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
wt_ctl.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wt_ctl.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wt_ctl.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wt_mux.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
wt_mux.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wt_mux.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
wt_mux.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
wt_mux.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
wt_mux.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
wt_mux.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wt_mux.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
wt_mux.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpga_arty.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
fpga_arty.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpga_arty.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
fpga_arty.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
fpga_arty.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
fpga_arty.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
fpga_arty.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpga_arty.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
fpga_arty.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
d_mem.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
d_mem.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
d_mem.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
d_mem.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
d_mem.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
d_mem.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
d_mem.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
d_mem.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
d_mem.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
text.mem=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Memory File)
text.mem=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
text.mem=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
text.mem=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
text.mem=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
text.mem=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
text.mem=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
text.mem=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_3.mem=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Memory File)
data_3.mem=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_3.mem=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
data_3.mem=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
data_3.mem=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
data_3.mem=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
data_3.mem=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_3.mem=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_2.mem=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Memory File)
data_2.mem=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_2.mem=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
data_2.mem=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
data_2.mem=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
data_2.mem=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
data_2.mem=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_2.mem=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_0.mem=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Memory File)
data_0.mem=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_0.mem=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
data_0.mem=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
data_0.mem=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
data_0.mem=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
data_0.mem=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_0.mem=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_1.mem=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Memory File)
data_1.mem=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_1.mem=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
data_1.mem=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
data_1.mem=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
data_1.mem=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
data_1.mem=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
data_1.mem=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
DATAFLOW_VIEWER_SETTINGS:(string) DEFAULT_VALUE ()==CURRENT_VALUE (min_width=16)
DEFINE:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
DESIGN_MODE:(enum) DEFAULT_VALUE (RTL)==CURRENT_VALUE (RTL)
EDIF_EXTRA_SEARCH_PATHS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
ELAB_LINK_DCPS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ELAB_LOAD_TIMING_CONSTRAINTS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
GENERIC:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCLUDE_DIRS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
LIB_MAP_FILE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
LOOP_COUNT:(int) DEFAULT_VALUE (1000)==CURRENT_VALUE (1000)
NAME:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
TOP:(string) DEFAULT_VALUE ()==CURRENT_VALUE (fpga_arty)
TOP_AUTO_SET:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (0)
VERILOG_DEFINE:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
VERILOG_UPPERCASE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
VERILOG_VERSION:(enum) DEFAULT_VALUE (verilog_2001)==CURRENT_VALUE (verilog_2001)
VHDL_DEFINE:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
VHDL_VERSION:(enum) DEFAULT_VALUE (vhdl_2k)==CURRENT_VALUE (vhdl_2k)
clk_wiz_0.xci=GENERATE_FILES_FOR_REFERENCE (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
clk_wiz_0.xci=GENERATE_SYNTH_CHECKPOINT (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
clk_wiz_0.xci=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
clk_wiz_0.xci=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
clk_wiz_0.xci=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
clk_wiz_0.xci=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
clk_wiz_0.xci=REGISTERED_WITH_MANAGER (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (1)
clk_wiz_0.xci=SYNTH_CHECKPOINT_MODE (enum) :DEFAULT_VALUE (None)==CURRENT_VALUE (Singular)
clk_wiz_0.xci=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
clk_wiz_0.xci=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
clk_wiz_0.xci=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
clk_wiz_0.xci=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ARTY.xdc=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (XDC)
ARTY.xdc=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ARTY.xdc=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
ARTY.xdc=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
ARTY.xdc=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
ARTY.xdc=PROCESSING_ORDER (enum) :DEFAULT_VALUE (NORMAL)==CURRENT_VALUE (NORMAL)
ARTY.xdc=SCOPED_TO_CELLS (string*) :DEFAULT_VALUE ()==CURRENT_VALUE ()
ARTY.xdc=SCOPED_TO_REF (string) :DEFAULT_VALUE ()==CURRENT_VALUE ()
ARTY.xdc=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation)==CURRENT_VALUE (synthesis implementation)
ARTY.xdc=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ARTY.xdc=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
CONSTRS_TYPE:(enum) DEFAULT_VALUE (XDC)==CURRENT_VALUE (XDC)
NAME:(string) DEFAULT_VALUE (constrs_1)==CURRENT_VALUE (constrs_1)
TARGET_CONSTRS_FILE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ($PSRCDIR/)
TARGET_PART:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xc7a35ticsg324-1L)
tb_top_arty.sv=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (SystemVerilog)
tb_top_arty.sv=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
tb_top_arty.sv=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
tb_top_arty.sv=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
tb_top_arty.sv=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
tb_top_arty.sv=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
tb_top_arty.sv=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
tb_top_arty.sv=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
tb_top_arty.sv=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
32BIT:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
CONFIGURE_FOR_GUI_MODE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
DEFINE:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
FORCE_COMPILE_GLBL:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
FORCE_NO_COMPILE_GLBL:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
GENERATE_SCRIPTS_ONLY:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
GENERIC:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
HBS.CONFIGURE_DESIGN_FOR_HIER_ACCESS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
HW_EMU.DEBUG_MODE:(enum) DEFAULT_VALUE (wdb)==CURRENT_VALUE (wdb)
INCLUDE_DIRS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCREMENTAL:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
NAME:(string) DEFAULT_VALUE (sim_1)==CURRENT_VALUE (sim_1)
NL.CELL:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
NL.INCL_UNISIM_MODELS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
NL.PROCESS_CORNER:(string) DEFAULT_VALUE (slow)==CURRENT_VALUE (slow)
NL.RENAME_TOP:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
NL.SDF_ANNO:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
NL.WRITE_ALL_OVERRIDES:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
SIMMODEL_VALUE_CHECK:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
SIMULATOR_LAUNCH_MODE:(enum) DEFAULT_VALUE (off)==CURRENT_VALUE (off)
SOURCE_SET:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
SYSTEMC_INCLUDE_DIRS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
TOP:(string) DEFAULT_VALUE ()==CURRENT_VALUE (tb_top_arty)
TOP_AUTO_SET:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (0)
TOP_LIB:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xil_defaultlib)
TRANSPORT_INT_DELAY:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
TRANSPORT_PATH_DELAY:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
UNIFAST:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
VERILOG_DEFINE:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
VERILOG_UPPERCASE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
VHDL_DEFINE:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
XELAB.DLL:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.COMPILE.TCL.PRE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XSC.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XSC.MT_LEVEL:(enum) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
XSIM.COMPILE.XVHDL.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XVHDL.NOSORT:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.COMPILE.XVHDL.RELAX:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.COMPILE.XVLOG.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XVLOG.NOSORT:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.COMPILE.XVLOG.RELAX:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.ELABORATE.COVERAGE.CELLDEFINE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.ELABORATE.COVERAGE.DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.ELABORATE.COVERAGE.LIBRARY:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.ELABORATE.COVERAGE.NAME:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.ELABORATE.COVERAGE.TYPE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.ELABORATE.DEBUG_LEVEL:(enum) DEFAULT_VALUE (typical)==CURRENT_VALUE (typical)
XSIM.ELABORATE.LINK.C:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.ELABORATE.LINK.SYSC:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.ELABORATE.LOAD_GLBL:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
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REPORTS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE (impl_1#impl_1_route_report_drc_0)
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STATISTICS.GTX:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
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STATISTICS.PCIE:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STATISTICS.PHASER:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STATISTICS.PLL:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
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STATISTICS.PS7:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
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STATISTICS.SIGNALS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STATISTICS.TOTAL_POWER:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STATISTICS.TRANSCEIVER:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STATISTICS.XADC:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
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VIEW.TYPE:(string) DEFAULT_VALUE (Graph)==CURRENT_VALUE (Graph)
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REPORTS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE (impl_1#impl_1_route_report_timing_summary_0)
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STATISTICS.TNS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STATISTICS.TPWS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STATISTICS.WBSS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STATISTICS.WHS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STATISTICS.WNS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
VIEW.ORIENTATION:(string) DEFAULT_VALUE (Horizontal)==CURRENT_VALUE (Horizontal)
VIEW.TYPE:(string) DEFAULT_VALUE (Table)==CURRENT_VALUE (Table)
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REPORTS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE (synth_1#synth_1_synth_report_utilization_0)
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VIEW.TYPE:(string) DEFAULT_VALUE (Graph)==CURRENT_VALUE (Graph)
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VIEW.ORIENTATION:(string) DEFAULT_VALUE (Horizontal)==CURRENT_VALUE (Horizontal)
VIEW.TYPE:(string) DEFAULT_VALUE (Graph)==CURRENT_VALUE (Graph)