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armv7a: change memory attributes
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Set memory as shareable and enable write-allocate - needed for SMP
Change AP values of 110 into 111 - previous value is deprecated

JIRA: RTOS-796
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@jmaksymowicz @Darchiv
jmaksymowicz authored and Darchiv committed Jul 2, 2024
1 parent 2245c6a commit 010dab8
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Showing 2 changed files with 79 additions and 65 deletions.
104 changes: 54 additions & 50 deletions hal/armv7a/pmap.c
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Original file line number Diff line number Diff line change
Expand Up @@ -37,25 +37,27 @@ extern unsigned int _etext;

#define SIZE_EXTEND_BSS 18 * SIZE_PAGE

#define TT2S_ATTR_MASK 0xfff
#define TT2S_NOTGLOBAL 0x800
#define TT2S_SHAREABLE 0x400
#define TT2S_READONLY 0x200
#define TT2S_ATTR_MASK 0xfff
#define TT2S_NOTGLOBAL 0x800
#define TT2S_SHAREABLE 0x400
#define TT2S_SMALLPAGE 0x002
#define TT2S_EXECNEVER 0x001
/* Memory region attributes (encodes TT2 descriptor bits [11:0]: ---T EX-- CB--) */
#define TT2S_ORDERED 0x000
#define TT2S_SHARED_DEV 0x004
#define TT2S_CACHED 0x00c
#define TT2S_NOTCACHED 0x040
#define TT2S_NOTSHARED_DEV 0x080
#define TT2S_PL0ACCESS 0x020
#define TT2S_ACCESSFLAG 0x010
#define TT2S_SMALLPAGE 0x002
#define TT2S_EXECNEVER 0x001

#define TT2S_CACHING_ATTR TT2S_CACHED

/* Page dirs & tables are write-back no write-allocate inner/outer cachable */
#define TTBR_CACHE_CONF (1 | (1 << 6) | (3 << 3))
#define TT2S_ORDERED 0x000
#define TT2S_SHARED_DEV 0x004
#define TT2S_CACHED 0x04c
#define TT2S_NOTCACHED 0x040
#define TT2S_NOTSHARED_DEV 0x080
/* Access permission bits AP[2:0] */
#define TT2S_READONLY 0x200
#define TT2S_PL0ACCESS 0x020
#define TT2S_ACCESSFLAG 0x010

#define TT2S_COMMON_ATTR (TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHAREABLE)
#define TT2S_CACHING_ATTR TT2S_CACHED

/* Page dirs & tables are write-back no write-allocate inner/outer cacheable, shareable */
#define TTBR_CACHE_CONF (1 | (1 << 6) | (3 << 3) | 2)

#define ID_PDIR(vaddr) (((ptr_t)(vaddr) >> 20))
#define ID_PTABLE(vaddr) (((ptr_t)(vaddr) >> 12) & 0x3ff)
Expand Down Expand Up @@ -85,40 +87,42 @@ struct {
static const char *const marksets[4] = { "BBBBBBBBBBBBBBBB", "KYCPMSHKKKKKKKKK", "AAAAAAAAAAAAAAAA", "UUUUUUUUUUUUUUUU" };


/* clang-format off */
static const u16 attrMap[] = {
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_CACHING_ATTR | TT2S_EXECNEVER | TT2S_READONLY,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_READONLY,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_CACHING_ATTR | TT2S_READONLY,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV | TT2S_READONLY,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_CACHING_ATTR | TT2S_EXECNEVER,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV | TT2S_EXECNEVER,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_CACHING_ATTR,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV,
TT2S_SMALLPAGE | TT2S_CACHING_ATTR | TT2S_EXECNEVER | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_CACHING_ATTR | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_SHARED_DEV | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_CACHING_ATTR | TT2S_EXECNEVER | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_CACHING_ATTR | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_NOTCACHED | TT2S_EXECNEVER | TT2S_READONLY,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_READONLY,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_NOTCACHED | TT2S_READONLY,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV | TT2S_READONLY,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_NOTCACHED | TT2S_EXECNEVER,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV | TT2S_EXECNEVER,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_NOTCACHED,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV,
TT2S_SMALLPAGE | TT2S_NOTCACHED | TT2S_EXECNEVER | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_NOTCACHED | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_SHARED_DEV | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_NOTCACHED | TT2S_EXECNEVER | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_NOTCACHED | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_SMALLPAGE | TT2S_ACCESSFLAG | TT2S_SHARED_DEV | TT2S_PL0ACCESS | TT2S_NOTGLOBAL
TT2S_COMMON_ATTR | TT2S_CACHING_ATTR | TT2S_EXECNEVER | TT2S_READONLY,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_READONLY,
TT2S_COMMON_ATTR | TT2S_CACHING_ATTR | TT2S_READONLY,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_READONLY,
TT2S_COMMON_ATTR | TT2S_CACHING_ATTR | TT2S_EXECNEVER,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_EXECNEVER,
TT2S_COMMON_ATTR | TT2S_CACHING_ATTR,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV,
TT2S_COMMON_ATTR | TT2S_CACHING_ATTR | TT2S_EXECNEVER | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_CACHING_ATTR | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_CACHING_ATTR | TT2S_EXECNEVER | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_CACHING_ATTR | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_NOTCACHED | TT2S_EXECNEVER | TT2S_READONLY,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_READONLY,
TT2S_COMMON_ATTR | TT2S_NOTCACHED | TT2S_READONLY,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_READONLY,
TT2S_COMMON_ATTR | TT2S_NOTCACHED | TT2S_EXECNEVER,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_EXECNEVER,
TT2S_COMMON_ATTR | TT2S_NOTCACHED,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV,
TT2S_COMMON_ATTR | TT2S_NOTCACHED | TT2S_EXECNEVER | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_NOTCACHED | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_READONLY | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_NOTCACHED | TT2S_EXECNEVER | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_EXECNEVER | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_NOTCACHED | TT2S_PL0ACCESS | TT2S_NOTGLOBAL,
TT2S_COMMON_ATTR | TT2S_SHARED_DEV | TT2S_PL0ACCESS | TT2S_NOTGLOBAL
};
/* clang-format on */


static void _pmap_asidAlloc(pmap_t *pmap)
Expand Down
40 changes: 25 additions & 15 deletions hal/armv7a/zynq7000/_init.S
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,16 @@
#define PA_SLCR 0xf8000000
#define PA_TTC 0xf8001000

/* Attributes for kernel pages:
* Small page, XN = 0 (allow Execute), TEX = 1 C = 1 B = 1 (Outer and Inner Write-Back, Write-Allocate),
* AP = 0x1 (R/W from PL1 only), S = 1 (Shareable), nG = 0 (Global) */
#define KERNEL_PAGE_ATTR 0x45E

/* Attributes for device pages:
* Small page, XN = 1 (Execute Never), TEX = 0 C = 0 B = 1 (Shared Device),
* AP = 0x1 (R/W from PL1 only), S = 0 (unused), nG = 0 (Global) */
#define DEVICE_PAGE_ATTR 0x17

.arm

.section .init, "ax"
Expand Down Expand Up @@ -206,14 +216,14 @@ clear_ttls:
/* Exceptions vectors TTL2 entry */
/* Map V 0xffff0000 -> P 0x00100000 */
ldr r0, =(PA_OF(VA_TTL2_EXC) + (0x3f0 << 2)) /* Entry address: 4 entries from the end in last TTL2 in pmap_common.excptab */
orr r1, r8, #0x1a /* Ptr to physical address. Attributes: XN = 0, B = 0, C = 0, AP = 0x3, TEX = 0 */
orr r1, r8, #0x1a /* Ptr to physical address. Attributes: XN = 0, B = 0, C = 0, AP = 0x1, TEX = 0 */
str r1, [r0] /* Fill TTL2 entry */


/* Stack TTL2 entry */
/* Map V 0xfffff000 -> P PA_STACK */
ldr r0, =(PA_OF(VA_TTL2_EXC) + (0x3ff << 2)) /* Entry address: the last entry in 4 TTL2 in pmap_common.excptab */
ldr r1, =((PA_STACK & ~0xfff) | 0x1e) /* Ptr to physical address. Attributes: XN = 0, B = 1, C = 1, AP = 0x3, TEX = 0 */
ldr r1, =((PA_STACK & ~0xfff) | KERNEL_PAGE_ATTR)
str r1, [r0]

/* Set vector table pointer to virtual address */
Expand All @@ -223,8 +233,8 @@ clear_ttls:

/* Kernel TTL2 entries (pmap_common.kptab) */
ldr r0, =PA_OF(VA_TTL2_K)
ldr r1, =((PA_KERNEL & ~0xfff) + (1024 * SIZE_PAGE) | 0x1e) /* Ptr past-the-end of physical addresses. Attributes: XN = 0, B = 1, C = 1, AP = 0x3, TEX = 0 */
mov r2, #(4 * 1024) /* size of pmap_common.kptab, it contains 4 TTL2 */
ldr r1, =((PA_KERNEL & ~0xfff) + (1024 * SIZE_PAGE) | KERNEL_PAGE_ATTR) /* Ptr past-the-end of physical addresses */
mov r2, #(4 * 1024) /* size of pmap_common.kptab, it contains 4 TTL2 */
/* Map the whole kernel memory */
kernel_ttl2:
subs r2, r2, #4
Expand All @@ -237,7 +247,8 @@ kernel_ttl2:
ldr r1, =(pmap_common - VADDR_KERNEL) /* offset of pmap_common.kpdir */
add r0, r1, lsr #10 /* r0 = PA_OF(VA_TTL2_K) + (offset of: pmap_common.kpdir >> 10) */
add r1, r1, #PA_KERNEL /* physical address of pmap_common.kpdir */
orr r1, r1, #0x1f /* Attributes: XN = 1, B = 1, C = 1, AP = 0x3, TEX = 0 */
ldr r3, =#(KERNEL_PAGE_ATTR | 0x01) /* Attributes: default + XN bit */
orr r1, r1, r3
mov r2, #0x1000
bl _cpy4
bl _cpy4
Expand All @@ -254,38 +265,37 @@ kernel_ttl2:
lsl r0, #2
ldr r1, =PA_OF(VA_TTL2_K)
add r0, r0, r1
ldr r1, =(PA_UART0 | 0x12)
ldr r1, =(PA_UART0 | DEVICE_PAGE_ATTR)
str r1, [r0], #4

/* Map UART1 4KB P 0xE0001000 -> V CEIL(_end + SIZE_PAGE, SIZE_PAGE) */
ldr r1, =(PA_UART1 | 0x12)
ldr r1, =(PA_UART1 | DEVICE_PAGE_ATTR)
str r1, [r0], #4

/* Map GIC 16 KB after UARTs */
mrc p15, 4, r1, c15, c0, 0 /* Get GIC paddr */
lsr r1, #16
lsl r1, #16
orr r1, r1, #0x12
orr r1, r1, #DEVICE_PAGE_ATTR
mov r2, #(1 << 12)
bl _cpy4

/* Map SLCR after GIC */
ldr r1, =(PA_SLCR | 0x12)
ldr r1, =(PA_SLCR | DEVICE_PAGE_ATTR)
str r1, [r0], #4

/* Map TTC after SLCR */
ldr r1, =(PA_TTC | 0x12)
ldr r1, =(PA_TTC | DEVICE_PAGE_ATTR)
str r1, [r0], #4


/* Initialize MMU */
mov r1, #1
mcr p15, 0, r1, c2, c0, 2 /* Write Translation Table Base Control Register */
mcr p15, 0, r1, c2, c0, 2 /* Write Translation Table Base Control Register */
ldr r1, =PA_OF(VA_TTL1)
orr r1, r1, #(1 | (1 << 6)) /* Inner cacheability */
orr r1, r1, #(3 << 3) /* Outer cacheability */
mcr p15, 0, r1, c2, c0, 0 /* Write Translation Table Base Register 0 */
mcr p15, 0, r1, c2, c0, 1 /* Write Translation Table Base Register 1 */
orr r1, r1, #(1 | (1 << 6) | (3 << 3) | 2) /* Inner and outer cacheability */
mcr p15, 0, r1, c2, c0, 0 /* Write Translation Table Base Register 0 */
mcr p15, 0, r1, c2, c0, 1 /* Write Translation Table Base Register 1 */

/* Set all Domains to Client */
ldr r1, =0x55555555
Expand Down

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