riscv: rename sbadaddr to stval

RISC-V Privileged Architectures V1.10 renamed and generalized sbadaddr
to stval. binutils >= 2.43 dropped support for sbadaddr alias.

JIRA: RTOS-913

hal/riscv64/_interrupts.S

@@ -422,10 +422,10 @@ _interrupts_exceptionFpu:
 	tail _interrupts_returnUnlocked
 
 _interrupts_exceptionNotFpu:
-	csrr s3, sbadaddr
+	csrr s3, stval
 	/* Save sscratch to be able to get hart ID */
 	csrr s5, sscratch
-	sd s3, 256(sp)   /* sbadaddr */
+	sd s3, 256(sp)   /* stval */
 	sd s5, 272(sp)
 
 	mv a1, sp

hal/riscv64/arch/cpu.h

@@ -162,7 +162,7 @@ typedef struct {
 	u64 ksp;
 	u64 sstatus;
 	u64 sepc;
-	u64 sbadaddr;
+	u64 stval;
 	u64 scause;
 	u64 sscratch;
 
@@ -296,7 +296,7 @@ void hal_cpuRemoteFlushTLB(u32 asid, const void *vaddr, size_t size);
 static inline void *hal_cpuGetFaultAddr(void)
 {
 	u64 badaddress;
-	badaddress = csr_read(sbadaddr);
+	badaddress = csr_read(stval);
 	return (void *)badaddress;
 }
 #endif

hal/riscv64/exceptions.c

@@ -101,7 +101,7 @@ void hal_exceptionsDumpContext(char *buff, exc_context_t *ctx, int n)
 	i += hal_i2s(" sstatus : ", &buff[i], (u64)ctx->sstatus, 16, 1);
 	i += hal_i2s(" sepc : ", &buff[i], (u64)ctx->sepc, 16, 1);
 	buff[i++] = '\n';
-	i += hal_i2s(" sbaddaddr : ", &buff[i], (u64)ctx->sbadaddr, 16, 1);
+	i += hal_i2s(" stval : ", &buff[i], (u64)ctx->stval, 16, 1);
 	i += hal_i2s(" scause : ", &buff[i], (u64)ctx->scause, 16, 1);
 	i += hal_i2s(" sscratch : ", &buff[i], (u64)ctx->sscratch, 16, 1);
 	buff[i++] = '\n';
@@ -164,7 +164,7 @@ int hal_exceptionsFaultType(unsigned int n, exc_context_t *ctx)
 
 inline void *hal_exceptionsFaultAddr(unsigned int n, exc_context_t *ctx)
 {
-	return (void *)ctx->sbadaddr;
+	return (void *)ctx->stval;
 }