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hal/sparcv8leon3: refactor timer register definitions
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JIRA: RTOS-885
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@lukileczo
lukileczo committed Aug 7, 2024
1 parent 1476a02 commit cbfee0e
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Showing 3 changed files with 24 additions and 74 deletions.
23 changes: 0 additions & 23 deletions hal/sparcv8leon3/gaisler/gr712rc/gr712rc.h
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Expand Up @@ -29,29 +29,6 @@
#include "include/arch/sparcv8leon3/gr712rc/gr712rc.h"


/* Timer registers */

#define GPT_SCALER 0 /* Scaler value register : 0x00 */
#define GPT_SRELOAD 1 /* Scaler reload value register : 0x04 */
#define GPT_CONFIG 2 /* Configuration register : 0x08 */

#define GPT_TCNTVAL1 4 /* Timer 1 counter value reg : 0x10 */
#define GPT_TRLDVAL1 5 /* Timer 1 reload value reg : 0x14 */
#define GPT_TCTRL1 6 /* Timer 1 control register : 0x18 */

#define GPT_TCNTVAL2 8 /* Timer 2 counter value reg : 0x20 */
#define GPT_TRLDVAL2 9 /* Timer 2 reload value reg : 0x24 */
#define GPT_TCTRL2 10 /* Timer 2 control register : 0x28 */

#define GPT_TCNTVAL3 12 /* Timer 3 counter value reg : 0x30 */
#define GPT_TRLDVAL3 13 /* Timer 3 reload value reg : 0x34 */
#define GPT_TCTRL3 14 /* Timer 3 control register : 0x38 */

#define GPT_TCNTVAL4 16 /* Timer 4 counter value reg : 0x40 */
#define GPT_TRLDVAL4 17 /* Timer 4 reload value reg : 0x44 */
#define GPT_TCTRL4 18 /* Timer 4 control register : 0x48 */


int gaisler_setIomuxCfg(u8 pin, u8 opt, u8 pullup, u8 pulldn);


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35 changes: 0 additions & 35 deletions hal/sparcv8leon3/gaisler/gr716/gr716.h
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Expand Up @@ -31,41 +31,6 @@

#define TIMER_IRQ 9

/* Timer registers */

#define GPT_SCALER 0 /* Scaler value register : 0x00 */
#define GPT_SRELOAD 1 /* Scaler reload value register : 0x04 */
#define GPT_CONFIG 2 /* Configuration register : 0x08 */
#define GPT_LATCHCFG 3 /* Latch configuration register : 0x0C */
#define GPT_TCNTVAL1 4 /* Timer 1 counter value reg : 0x10 */
#define GPT_TRLDVAL1 5 /* Timer 1 reload value reg : 0x14 */
#define GPT_TCTRL1 6 /* Timer 1 control register : 0x18 */
#define GPT_TLATCH1 7 /* Timer 1 latch register : 0x1C */
#define GPT_TCNTVAL2 8 /* Timer 2 counter value reg : 0x20 */
#define GPT_TRLDVAL2 9 /* Timer 2 reload value reg : 0x24 */
#define GPT_TCTRL2 10 /* Timer 2 control register : 0x28 */
#define GPT_TLATCH2 11 /* Timer 2 latch register : 0x2C */
#define GPT_TCNTVAL3 12 /* Timer 3 counter value reg : 0x30 */
#define GPT_TRLDVAL3 13 /* Timer 3 reload value reg : 0x34 */
#define GPT_TCTRL3 14 /* Timer 3 control register : 0x38 */
#define GPT_TLATCH3 15 /* Timer 3 latch register : 0x3C */
#define GPT_TCNTVAL4 16 /* Timer 4 counter value reg : 0x40 */
#define GPT_TRLDVAL4 17 /* Timer 4 reload value reg : 0x44 */
#define GPT_TCTRL4 18 /* Timer 4 control register : 0x48 */
#define GPT_TLATCH4 19 /* Timer 4 latch register : 0x4C */
#define GPT_TCNTVAL5 20 /* Timer 5 counter value reg : 0x50 */
#define GPT_TRLDVAL5 21 /* Timer 5 reload value reg : 0x54 */
#define GPT_TCTRL5 22 /* Timer 5 control register : 0x58 */
#define GPT_TLATCH5 23 /* Timer 5 latch register : 0x5C */
#define GPT_TCNTVAL6 24 /* Timer 6 counter value reg : 0x60 */
#define GPT_TRLDVAL6 25 /* Timer 6 reload value reg : 0x64 */
#define GPT_TCTRL6 26 /* Timer 6 control register : 0x68 */
#define GPT_TLATCH6 27 /* Timer 6 latch register : 0x6C */
#define GPT_TCNTVAL7 28 /* Timer 7 counter value reg : 0x70 */
#define GPT_TRLDVAL7 29 /* Timer 7 reload value reg : 0x74 */
#define GPT_TCTRL7 30 /* Timer 7 control register : 0x78 */
#define GPT_TLATCH7 31 /* Timer 7 latch register : 0x7C */


extern int _gr716_getIomuxCfg(u8 pin, u8 *opt, u8 *pullup, u8 *pulldn);

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40 changes: 24 additions & 16 deletions hal/sparcv8leon3/gaisler/timer.c
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Expand Up @@ -34,15 +34,21 @@
#define TIMER_INT_PENDING (1 << 4)
#define TIMER_CHAIN (1 << 5)

/* Timer registers */

/* clang-format off */
#define GPT_SCALER 0 /* Scaler value register : 0x00 */
#define GPT_SRELOAD 1 /* Scaler reload value register : 0x04 */
#define GPT_CONFIG 2 /* Configuration register : 0x08 */
#define GPT_LATCHCFG 3 /* Latch configuration register : 0x0C */
#define GPT_TCNTVAL(n) (n * 4) /* Timer n counter value reg (n=1,2,...) : 0xn0 */
#define GPT_TRLDVAL(n) ((n * 4) + 1) /* Timer n reload value register : 0xn4 */
#define GPT_TCTRL(n) ((n * 4) + 2) /* Timer n control register : 0xn8 */
#define GPT_TLATCH(n) ((n * 4) + 3) /* Timer n latch register : 0xnC */

enum { timer1 = 0, timer2, timer3, timer4 };
#define TIMER_DEFAULT 1

/* clang-format on */


struct {
static struct {
volatile u32 *timer0_base;
intr_handler_t handler;
volatile time_t jiffies;
Expand All @@ -53,14 +59,14 @@ struct {

static int _timer_irqHandler(unsigned int irq, cpu_context_t *ctx, void *data)
{
volatile u32 st = *(timer_common.timer0_base + GPT_TCTRL1) & TIMER_INT_PENDING;
volatile u32 st = *(timer_common.timer0_base + GPT_TCTRL(TIMER_DEFAULT)) & TIMER_INT_PENDING;

if (st != 0) {
++timer_common.jiffies;
/* Clear irq status - set & clear to handle different GPTIMER core versions */
*(timer_common.timer0_base + GPT_TCTRL1) |= TIMER_INT_PENDING;
*(timer_common.timer0_base + GPT_TCTRL(TIMER_DEFAULT)) |= TIMER_INT_PENDING;
hal_cpuDataStoreBarrier();
*(timer_common.timer0_base + GPT_TCTRL1) &= ~TIMER_INT_PENDING;
*(timer_common.timer0_base + GPT_TCTRL(TIMER_DEFAULT)) &= ~TIMER_INT_PENDING;
hal_cpuDataStoreBarrier();
}

Expand All @@ -70,7 +76,7 @@ static int _timer_irqHandler(unsigned int irq, cpu_context_t *ctx, void *data)

static inline void timer_setReloadValue(int timer, u32 val)
{
*(timer_common.timer0_base + GPT_TRLDVAL1 + timer * 4) = val;
*(timer_common.timer0_base + GPT_TRLDVAL(timer)) = val;
}


Expand Down Expand Up @@ -124,23 +130,25 @@ char *hal_timerFeatures(char *features, unsigned int len)

void _hal_timerInit(u32 interval)
{
volatile u32 st;

timer_common.jiffies = 0;
timer_common.timer0_base = VADDR_GPTIMER0;

/* Disable timer interrupts - bits cleared when written 1 */
volatile u32 st = *(timer_common.timer0_base + GPT_TCTRL1) & (TIMER_INT_ENABLE | TIMER_INT_PENDING);
*(timer_common.timer0_base + GPT_TCTRL1) = st;
st = *(timer_common.timer0_base + GPT_TCTRL(TIMER_DEFAULT)) & (TIMER_INT_ENABLE | TIMER_INT_PENDING);
*(timer_common.timer0_base + GPT_TCTRL(TIMER_DEFAULT)) = st;
/* Disable timer */
*(timer_common.timer0_base + GPT_TCTRL1) = 0;
*(timer_common.timer0_base + GPT_TCTRL(TIMER_DEFAULT)) = 0;
/* Reset counter and reload value */
*(timer_common.timer0_base + GPT_TCNTVAL1) = 0;
*(timer_common.timer0_base + GPT_TRLDVAL1) = 0;
*(timer_common.timer0_base + GPT_TCNTVAL(TIMER_DEFAULT)) = 0;
timer_setReloadValue(TIMER_DEFAULT, 0);

timer_common.handler.f = NULL;
timer_common.handler.n = TIMER_IRQ;
timer_common.handler.data = NULL;

timer_setPrescaler(timer1, interval);
timer_setPrescaler(TIMER_DEFAULT, interval);

hal_spinlockCreate(&timer_common.sp, "timer");
timer_common.handler.f = _timer_irqHandler;
Expand All @@ -150,5 +158,5 @@ void _hal_timerInit(u32 interval)

/* Enable timer and interrupts */
/* Load reload value into counter register */
*(timer_common.timer0_base + GPT_TCTRL1) |= TIMER_ENABLE | TIMER_INT_ENABLE | TIMER_LOAD | TIMER_PERIODIC;
*(timer_common.timer0_base + GPT_TCTRL(TIMER_DEFAULT)) |= TIMER_ENABLE | TIMER_INT_ENABLE | TIMER_LOAD | TIMER_PERIODIC;
}

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