armv7m/imxrt117x: add CCM shared GPR registers

JIRA: NIL-441

hal/armv7m/imxrt/117x/imxrt117x.c

@@ -777,6 +777,31 @@ static int _imxrt_getIOlpsrGpr(int which, unsigned int *what)
 }
 
 
+static int _imxrt_setSharedGpr(int which, unsigned int what)
+{
+	if ((which < 0) || (which > 7)) {
+		return -EINVAL;
+	}
+
+	*(imxrt_common.ccm + 0x1200 + which * 0x8) = what;
+	hal_cpuDataSyncBarrier();
+
+	return  0;
+}
+
+
+static int _imxrt_getSharedGpr(int which, unsigned int *what)
+{
+	if ((which < 0) || (which > 7) || (what == NULL)) {
+		return -EINVAL;
+	}
+
+	*what = *(imxrt_common.ccm + 0x1200 + which * 0x8);
+
+	return 0;
+}
+
+
 int hal_platformctl(void *ptr)
 {
 	platformctl_t *data = ptr;
@@ -920,6 +945,18 @@ int hal_platformctl(void *ptr)
 			}
 			break;
 
+		case pctl_sharedGpr:
+			if (data->action == pctl_set) {
+				ret = _imxrt_setSharedGpr(data->iogpr.field, data->iogpr.val);
+			}
+			else if (data->action == pctl_get) {
+				ret = _imxrt_getSharedGpr(data->iogpr.field, &t);
+				if (ret == 0) {
+					data->iogpr.val = t;
+				}
+			}
+			break;
+
 		default:
 			break;
 	}

include/arch/armv7m/imxrt/11xx/imxrt1170.h

@@ -316,7 +316,7 @@ enum { cti0_err_irq = 17 + 16, cti1_err_irq, core_irq, lpuart1_irq, lpuart2_irq,
 typedef struct {
 	enum { pctl_set = 0, pctl_get } action;
 	enum { pctl_devclock = 0, pctl_iogpr, pctl_iolpsrgpr, pctl_iomux, pctl_iopad, pctl_ioisel, pctl_reboot, pctl_devcache,
-		pctl_lpcg, pctl_cleanInvalDCache, pctl_resetSlice } type;
+		pctl_lpcg, pctl_cleanInvalDCache, pctl_resetSlice, pctl_sharedGpr } type;
 
 	union {
 		struct {