zynq7000: SMP kernel #548
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zynq7000: SMP kernel #548
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Unit Test Results7 460 tests +724 6 745 ✅ +695 39m 33s ⏱️ + 6m 14s Results for commit b1884db. ± Comparison against base commit 47ac14e. This pull request removes 20 and adds 744 tests. Note that renamed tests count towards both.♻️ This comment has been updated with latest results. |
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agkaminski
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May 24, 2024
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agkaminski
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May 27, 2024
14 tasks
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Reverted change that activated L2 cache - it caused stability problems in some tests. I haven't found the reason for it yet. Because it's not necessary for SMP I think we should do it in a different PR. EDIT: it didn't help, only reduced frequency of failing |
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Darchiv
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Jun 25, 2024
Move memory barrier in spinlock clear operation zynq7000: Add memory barriers to SLCR locking/unlocking JIRA: RTOS-796
Page directories were previously 0x4000 bytes, but the upper half was never used by the hardware - only by pmap_resolve(). pmap_resolve() behavior was modified to closer align with how hardware resolves virtual memory addresses. JIRA: RTOS-796
Add scheduler lock Add TLB management broadcast functions Implement correct CPU ID and CPU count functions Add inter-processor interrupt Add core count to CPU info print at startup JIRA: RTOS-796
Set memory as shareable and enable write-allocate - needed for SMP Change AP values of 110 into 111 - previous value is deprecated JIRA: RTOS-796
Activate SCU and cache/TLB mainenance broadcast JIRA: RTOS-796
Allow interrupts to run on any core Schedule timer interrupt in a round-robin fashion across both cores Adjust timer to keep the current scheduling period on both cores JIRA: RTOS-796
JIRA: RTOS-796
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Darchiv
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Jul 2, 2024
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Allows tasks to be scheduled on both CPU cores on zynq7000 platform.
Description
NOTE: the corresponding PR in PLO must be merged first - otherwise on zynq7000 kernel will hang waiting for other CPU cores which will never start.
Code is capable of detecting number of available CPUs at runtime, the
NUM_CPUSconstant is used as maximum number of CPUs to prepare for.One change was made not related to SMP: size of page directories was changed from
0x4000bytes to0x2000bytes, as the upper half was unnecessaryMemory attributes were changed in common armv7a code, which affects imx6ull (but should not cause significant change).
Using SMP on armv7a9-zynq7000-qemu causes drastic slowdown (about 4x-5x slower) when executing single-core workloads. This is because under QEMU the idle thread creates a lot of load on the host CPU, as well as contention on the timer spinlock. This slowdown does not occur on real hardware. For this reason I suggest limiting QEMU to emulating only one core, as we can test SMP configurations on real hardware.
Motivation and Context
Types of changes
How Has This Been Tested?
Checklist:
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