add riscv64-noelv target

hal/riscv64/Makefile

@@ -4,10 +4,10 @@
 # Copyright 2018, 2020, 2024 Phoenix Systems
 #
 
-OBJS += $(addprefix $(PREFIX_O)hal/riscv64/, _init.o _string.o _interrupts.o hal.o spinlock.o interrupts.o cpu.o pmap.o \
-dtb.o timer.o string.o exceptions.o plic.o sbi.o)
+OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/, _init.o _cache.o _string.o _interrupts.o hal.o spinlock.o interrupts.o \
+	cpu.o pmap.o dtb.o timer.o string.o exceptions.o plic.o sbi.o)
 
-CFLAGS += -Ihal/riscv64
+include hal/$(TARGET_SUFF)/$(TARGET_SUBFAMILY)/Makefile
 
-OBJS += $(PREFIX_O)hal/riscv64/console.o
+CFLAGS += -Ihal/$(TARGET_SUFF) -Ihal/$(TARGET_SUFF)/$(TARGET_SUBFAMILY)
 

hal/riscv64/_cache.S

@@ -0,0 +1,78 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system kernel
+ *
+ * riscv64 cache management
+ *
+ * Copyright 2024 Phoenix Systems
+ * Author: Lukasz Leczkowski
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#define __ASSEMBLY__
+
+#include "asm-macros.h"
+#include <board_config.h>
+
+.text
+
+/* void hal_cpuDCacheInval(void *va, size_t size)
+ * va must have write access
+ */
+.global hal_cpuDCacheInval
+.type hal_cpuDCacheInval, @function
+hal_cpuDCacheInval:
+#ifdef DCACHE_BLOCK_SIZE
+	/* Align size to cache block size */
+	li a4, DCACHE_BLOCK_SIZE
+	addi a5, a4, -1
+	add a1, a1, a5
+	li a5, -DCACHE_BLOCK_SIZE
+	and a1, a1, a5
+
+	/* End address */
+	add a5, a1, a0
+	beq a0, a5, 2f
+
+1:
+	CBO_INVAL(REG_A0)
+	add a0, a0, a4
+	bgtu a5, a0, 1b
+
+2:
+#endif
+	ret
+.size hal_cpuDCacheInval, . - hal_cpuDCacheInval
+
+
+/* void hal_cpuDCacheFlush(void *va, size_t size)
+ * va must have write access
+ */
+.global hal_cpuDCacheFlush
+.type hal_cpuDCacheFlush, @function
+hal_cpuDCacheFlush:
+#ifdef DCACHE_BLOCK_SIZE
+	/* Align size to cache block size */
+	li a4, DCACHE_BLOCK_SIZE
+	addi a5, a4, -1
+	add a1, a1, a5
+	li a5, -DCACHE_BLOCK_SIZE
+	and a1, a1, a5
+
+	/* End address */
+	add a5, a1, a0
+	beq a0, a5, 2f
+
+1:
+	CBO_FLUSH(REG_A0)
+	add a0, a0, a4
+	bgtu a5, a0, 1b
+
+2:
+#endif
+	ret
+.size hal_cpuDCacheFlush, . - hal_cpuDCacheFlush

hal/riscv64/_init.S

@@ -103,8 +103,10 @@ syspage_cpy:
 	bltu t1, t2, syspage_cpy
 
 dtb:
-	mv a1, a2
-	call dtb_parse
+	mv s4, a2
+	mv a0, a2
+	call dtb_save
+	mv a0, s4
 	call _pmap_preinit
 
 _init_core:

hal/riscv64/_interrupts.S

@@ -99,8 +99,8 @@
 	sd sp, 232(sp)       /* ksp */
 
 	/* Check FPU status */
-	csrr t0, sstatus
-	srli t0, t0, 13
+	csrr s1, sstatus
+	srli t0, s1, 13
 
 	/* If FPU is clean or dirty, save context */
 	andi t0, t0, 2
@@ -148,15 +148,13 @@
 	csrc sstatus, t0
 	li t0, (2 << 13)
 	csrs sstatus, t0
-3:
 	csrr s1, sstatus
+3:
 	csrr s2, sepc
-	csrr s3, sbadaddr
 	csrr s4, scause
 
 	sd s1, 240(sp)   /* sstatus */
 	sd s2, 248(sp)   /* sepc */
-	sd s3, 256(sp)   /* sbadaddr */
 	sd s4, 264(sp)   /* scause */
 	sd tp, 280(sp)   /* tp */
 .endm
@@ -247,8 +245,6 @@
 
 	/* Restore task's stack pointer */
 	ld sp, 288(sp)
-
-	fence.i
 .endm
 
 
@@ -310,8 +306,7 @@ _interrupts_exception:
 	bnez t2, _interrupts_exceptionNotFpu
 
 	/* Get failing instruction */
-	csrr t0, sepc
-	lw t2, (t0)
+	csrr t2, stval
 	andi t0, t2, 0x7f
 
 	/* Check opcode:
@@ -427,8 +422,10 @@ _interrupts_exceptionFpu:
 	tail _interrupts_returnUnlocked
 
 _interrupts_exceptionNotFpu:
+	csrr s3, sbadaddr
 	/* Save sscratch to be able to get hart ID */
 	csrr s5, sscratch
+	sd s3, 256(sp)   /* sbadaddr */
 	sd s5, 272(sp)
 
 	mv a1, sp

hal/riscv64/arch/cpu.h

@@ -285,10 +285,10 @@ static inline int hal_cpuSupervisorMode(cpu_context_t *ctx)
 void hal_cpuRfenceI(void);
 
 
-void hal_cpuLocalFlushTLB(const struct _pmap_t *pmap, const void *vaddr);
+void hal_cpuLocalFlushTLB(u32 asid, const void *vaddr);
 
 
-void hal_cpuRemoteFlushTLB(const struct _pmap_t *pmap, const void *vaddr, size_t size);
+void hal_cpuRemoteFlushTLB(u32 asid, const void *vaddr, size_t size);
 
 
 /* Code used in disabled code vm/object.c - map_pageFault */

hal/riscv64/arch/pmap.h

@@ -22,6 +22,7 @@
 #define VADDR_MAX     0xffffffffffffffffL
 #define VADDR_USR_MAX VADDR_KERNEL
 
+#define VADDR_DTB 0xffffffffc0000000UL
 
 /* Architecure dependent page attributes */
 #define PGHD_PRESENT    0x01
@@ -82,6 +83,15 @@ typedef struct _pmap_t {
 addr_t pmap_getKernelStart(void);
 
 
+void *_pmap_halMap(addr_t paddr, void *va, size_t size, int attr);
+
+
+void *pmap_halMap(addr_t paddr, void *va, size_t size, int attr);
+
+
+void _pmap_halInit(void);
+
+
 #endif
 
 

hal/riscv64/asm-macros.h

@@ -0,0 +1,75 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system kernel
+ *
+ * Assembly macros
+ *
+ * Copyright 2024 Phoenix Systems
+ * Author: Lukasz Leczkowski
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#ifndef _ASM_MACROS_H_
+#define _ASM_MACROS_H_
+
+#define STR(x)  #x
+#define XSTR(x) STR(x)
+
+/* RISC-V registers */
+#define REG_ZERO 0
+#define REG_RA   1
+#define REG_SP   2
+#define REG_GP   3
+#define REG_TP   4
+#define REG_T0   5
+#define REG_T1   6
+#define REG_T2   7
+#define REG_S0   8
+#define REG_S1   9
+#define REG_A0   10
+#define REG_A1   11
+#define REG_A2   12
+#define REG_A3   13
+#define REG_A4   14
+#define REG_A5   15
+#define REG_A6   16
+#define REG_A7   17
+#define REG_S2   18
+#define REG_S3   19
+#define REG_S4   20
+#define REG_S5   21
+#define REG_S6   22
+#define REG_S7   23
+#define REG_S8   24
+#define REG_S9   25
+#define REG_S10  26
+#define REG_S11  27
+#define REG_T3   28
+#define REG_T4   29
+#define REG_T5   30
+#define REG_T6   31
+
+
+#define OPCODE_MISC_MEM 0xf
+#define FUNCT3_CBO      (0x2 << 12)
+
+/* clang-format off */
+
+/* Instructions supported from GCC 14 */
+#define CBO_INVAL(REG) \
+	.word ((REG & 0x1f) << 15) | FUNCT3_CBO | OPCODE_MISC_MEM
+
+#define CBO_CLEAN(REG) \
+	.word (1 << 20) | ((REG & 0x1f) << 15) | FUNCT3_CBO | OPCODE_MISC_MEM
+
+#define CBO_FLUSH(REG) \
+	.word (1 << 21) | ((REG & 0x1f) << 15) | FUNCT3_CBO | OPCODE_MISC_MEM
+
+
+/* clang-format on */
+
+#endif

hal/riscv64/cpu.c

@@ -373,9 +373,9 @@ void hal_cpuRfenceI(void)
 }
 
 
-void hal_cpuLocalFlushTLB(const struct _pmap_t *pmap, const void *vaddr)
+void hal_cpuLocalFlushTLB(u32 asid, const void *vaddr)
 {
-	(void)pmap; /* TODO: ASID support */
+	(void)asid; /* TODO: ASID support */
 
 	/* clang-format off */
 	__asm__ volatile (
@@ -388,18 +388,19 @@ void hal_cpuLocalFlushTLB(const struct _pmap_t *pmap, const void *vaddr)
 }
 
 
-void hal_cpuRemoteFlushTLB(const struct _pmap_t *pmap, const void *vaddr, size_t size)
+void hal_cpuRemoteFlushTLB(u32 asid, const void *vaddr, size_t size)
 {
-	(void)pmap; /* TODO: ASID support */
-
+	size_t i;
 	unsigned long hart_mask;
 
 	if (hal_cpuGetCount() > 1) {
 		hart_mask = (1 << hal_cpuGetCount()) - 1;
 		hal_sbiSfenceVma(hart_mask, 0, (unsigned long)vaddr, size);
 	}
 	else {
-		hal_cpuLocalFlushTLB(pmap, vaddr);
+		for (i = 0; i < size; i += SIZE_PAGE) {
+			hal_cpuLocalFlushTLB(asid, (void *)((unsigned long)vaddr + i));
+		}
 	}
 }